[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit C
|
From: |
Alistair Francis |
|
Subject: |
[Qemu-riscv] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR |
|
Date: |
Mon, 17 Jun 2019 18:31:08 -0700 |
Add a comment for the new mcountinhibit which conflicts with the
CSR_MUCOUNTEREN from version 1.09.1. This can be updated when we remove
1.09.1.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 47450a3cdb..11f971ad5d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -136,6 +136,7 @@
#define CSR_MCOUNTEREN 0x306
/* Legacy Counter Setup (priv v1.9.1) */
+/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
#define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321
#define CSR_MHCOUNTEREN 0x322
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c67d29e206..437387fd28 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -461,18 +461,20 @@ static int write_mcounteren(CPURISCVState *env, int
csrno, target_ulong val)
return 0;
}
+/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
+ if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver <
PRIV_VERSION_1_11_0) {
return -1;
}
*val = env->mcounteren;
return 0;
}
+/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
+ if (env->priv_ver > PRIV_VERSION_1_09_1 && env->priv_ver <
PRIV_VERSION_1_11_0) {
return -1;
}
env->mcounteren = val;
--
2.22.0
- [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 2/9] target/riscv: Add the privledge spec version 1.11.0, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 4/9] target/riscv: Set privledge spec 1.11.0 as default, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 5/9] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 6/9] target/riscv: Require either I or E base extension, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 7/9] target/riscv: Remove user version information, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 8/9] target/riscv: Add support for disabling/enabling Counters, Alistair Francis, 2019/06/17