Re: [PATCH v2 11/14] target/ppc: 405: Data Storage exception cleanup

[Cédric Le Goater]

On 1/19/22 07:13, David Gibson wrote:
> On Tue, Jan 18, 2022 at 03:44:45PM -0300, Fabiano Rosas wrote:
> > The 405 has no DSISR or DAR, so convert the trace entry to
> > trace_ppc_excp_print.
>
> I think it would be preferable to show ESR and DEAR here, which are
> very loosely equivalent to DSISR and DAR on 40x.  Might want to create
> a new trace point explicitly for this so the terminology is clear as well.

I changed registers to ESR and DEAR and updated commit log.

Trace point changes can come later. Some have become a bit redundant
with CPU_LOG_INT.

Thanks,

C.


> > Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> > ---
> >   target/ppc/excp_helper.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> > index 84ec7e094a..e4e513322c 100644
> > --- a/target/ppc/excp_helper.c
> > +++ b/target/ppc/excp_helper.c
> > @@ -465,7 +465,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> >           srr1 = SPR_40x_SRR3;
> >           break;
> >       case POWERPC_EXCP_DSI:       /* Data storage exception                   
> > */
> > -        trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
> > +        trace_ppc_excp_print("DSI");
> >           break;
> >       case POWERPC_EXCP_ISI:       /* Instruction storage exception            
> > */
> >           trace_ppc_excp_isi(msr, env->nip);