Re: [PATCH v2 13/14] target/ppc: 405: Program exception cleanup

[Cédric Le Goater]

On 1/19/22 13:54, Fabiano Rosas wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > On Tue, Jan 18, 2022 at 03:44:47PM -0300, Fabiano Rosas wrote:
> > > The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
> > > just a clean copy of the MSR.
> > >
> > > We're using the BookE Exception Syndrome Register which is different
> > > from the 405.
> >
> > Hrm.  We really do want to set the 40x ESR bits here, though.
>
> Well I wrote the code and nothing changed so I dropped it. Not sure if
> we are even raising these properly in the translation code. I'll take
> another look.

For instance, this ESR bit allows Linux to handle traps correctly in
some cases, like when CONFIG_DEBUG_VM=y :

@@ -488,7 +488,9 @@ static void powerpc_excp_40x(PowerPCCPU
             trace_ppc_excp_inval(env->nip);
             break;
         case POWERPC_EXCP_PRIV:
+            break;
         case POWERPC_EXCP_TRAP:
+            env->spr[SPR_40x_ESR] = ESR_PTR;
             break;
         default:
             cpu_abort(cs, "Invalid program exception %d. Aborting\n",


These could be reported to Linux :

/* On 4xx, the reason for the machine check or program exception
   is in the ESR. */
#define get_reason(regs)        ((regs)->esr)
#define REASON_FP               ESR_FP
#define REASON_ILLEGAL          (ESR_PIL | ESR_PUO)
#define REASON_PRIVILEGED       ESR_PPR
#define REASON_TRAP             ESR_PTR
#define REASON_PREFIXED         0
#define REASON_BOUNDARY         0


Thanks,

C.