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[PATCH 12/37] target/ppc: Implement Vector Compare Greater Than Quadword
From: |
matheus . ferst |
Subject: |
[PATCH 12/37] target/ppc: Implement Vector Compare Greater Than Quadword |
Date: |
Fri, 7 Jan 2022 15:56:28 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
vcmpgtsq: Vector Compare Greater Than Signed Quadword
vcmpgtuq: Vector Compare Greater Than Unsigned Quadword
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate/vmx-impl.c.inc | 49 +++++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 39730df32d..45649f7d1d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -388,11 +388,13 @@ VCMPGTSB 000100 ..... ..... ..... . 1100000110
@VC
VCMPGTSH 000100 ..... ..... ..... . 1101000110 @VC
VCMPGTSW 000100 ..... ..... ..... . 1110000110 @VC
VCMPGTSD 000100 ..... ..... ..... . 1111000111 @VC
+VCMPGTSQ 000100 ..... ..... ..... . 1110000111 @VC
VCMPGTUB 000100 ..... ..... ..... . 1000000110 @VC
VCMPGTUH 000100 ..... ..... ..... . 1001000110 @VC
VCMPGTUW 000100 ..... ..... ..... . 1010000110 @VC
VCMPGTUD 000100 ..... ..... ..... . 1011000111 @VC
+VCMPGTUQ 000100 ..... ..... ..... . 1010000111 @VC
VCMPNEB 000100 ..... ..... ..... . 0000000111 @VC
VCMPNEH 000100 ..... ..... ..... . 0001000111 @VC
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index bdb0b4370b..302ef4370a 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1155,6 +1155,55 @@ static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
return true;
}
+static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign)
+{
+ TCGv_i64 t0, t1;
+ TCGLabel *l1, *l2, *l3;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ t0 = tcg_temp_local_new_i64();
+ t1 = tcg_temp_local_new_i64();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ l3 = gen_new_label();
+
+ get_avr64(t0, a->vra, true);
+ get_avr64(t1, a->vrb, true);
+ tcg_gen_brcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t0, t1, l1);
+ tcg_gen_brcond_i64(sign ? TCG_COND_LT : TCG_COND_LTU, t0, t1, l2);
+
+ get_avr64(t0, a->vra, false);
+ get_avr64(t1, a->vrb, false);
+ tcg_gen_brcond_i64(TCG_COND_GTU, t0, t1, l1);
+ tcg_gen_br(l2);
+
+ gen_set_label(l1);
+ set_avr64(a->vrt, tcg_constant_i64(-1), true);
+ set_avr64(a->vrt, tcg_constant_i64(-1), false);
+ if (a->rc) {
+ tcg_gen_movi_i32(cpu_crf[6], 1 << 3);
+ }
+ tcg_gen_br(l3);
+
+ gen_set_label(l2);
+ set_avr64(a->vrt, tcg_constant_i64(0), true);
+ set_avr64(a->vrt, tcg_constant_i64(0), false);
+ if (a->rc) {
+ tcg_gen_movi_i32(cpu_crf[6], 1 << 1);
+ }
+
+ gen_set_label(l3);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+
+ return true;
+}
+
+TRANS(VCMPGTSQ, do_vcmpgtq, true)
+TRANS(VCMPGTUQ, do_vcmpgtq, false)
+
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
--
2.25.1
- Re: [PATCH 01/37] target/ppc: Introduce TRANS*FLAGS macros, (continued)
- [PATCH 03/37] target/ppc: Moved vector multiply high and low to decodetree, matheus . ferst, 2022/01/07
- [PATCH 02/37] target/ppc: moved vector even and odd multiplication to decodetree, matheus . ferst, 2022/01/07
- [PATCH 04/37] target/ppc: vmulh* instructions use gvec, matheus . ferst, 2022/01/07
- [PATCH 05/37] target/ppc: Implement vmsumcud instruction, matheus . ferst, 2022/01/07
- [PATCH 06/37] target/ppc: Implement vmsumudm instruction, matheus . ferst, 2022/01/07
- [PATCH 07/37] target/ppc: Move vexts[bhw]2[wd] to decodetree, matheus . ferst, 2022/01/07
- [PATCH 08/37] target/ppc: Implement vextsd2q, matheus . ferst, 2022/01/07
- [PATCH 09/37] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree, matheus . ferst, 2022/01/07
- [PATCH 10/37] target/ppc: Move Vector Compare Not Equal or Zero to decodetree, matheus . ferst, 2022/01/07
- [PATCH 12/37] target/ppc: Implement Vector Compare Greater Than Quadword,
matheus . ferst <=
- [PATCH 11/37] target/ppc: Implement Vector Compare Equal Quadword, matheus . ferst, 2022/01/07
- [PATCH 13/37] target/ppc: Implement Vector Compare Quadword, matheus . ferst, 2022/01/07
- [PATCH 14/37] target/ppc: implement vstri[bh][lr], matheus . ferst, 2022/01/07
- [PATCH 15/37] target/ppc: implement vclrlb, matheus . ferst, 2022/01/07
- [PATCH 16/37] target/ppc: implement vclrrb, matheus . ferst, 2022/01/07
- [PATCH 17/37] target/ppc: implement vcntmb[bhwd], matheus . ferst, 2022/01/07
- [PATCH 19/37] target/ppc: Move vsel and vperm/vpermr to decodetree, matheus . ferst, 2022/01/07
- [PATCH 18/37] target/ppc: implement vgnb, matheus . ferst, 2022/01/07
- [PATCH 20/37] target/ppc: Move xxsel to decodetree, matheus . ferst, 2022/01/07
- [PATCH 21/37] target/ppc: move xxperm/xxpermr to decodetree, matheus . ferst, 2022/01/07