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[PATCH 08/37] target/ppc: Implement vextsd2q
From: |
matheus . ferst |
Subject: |
[PATCH 08/37] target/ppc: Implement vextsd2q |
Date: |
Fri, 7 Jan 2022 15:56:24 -0300 |
From: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 18 ++++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 757791f0ac..1c935eeac8 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -426,6 +426,7 @@ VEXTSH2W 000100 ..... 10001 ..... 11000000010
@VX_tb
VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb
VEXTSH2D 000100 ..... 11001 ..... 11000000010 @VX_tb
VEXTSW2D 000100 ..... 11010 ..... 11000000010 @VX_tb
+VEXTSD2Q 000100 ..... 11011 ..... 11000000010 @VX_tb
## Vector Mask Manipulation Instructions
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index ec782c47ff..99606a8718 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1792,6 +1792,24 @@ TRANS(VEXTSB2D, do_vexts, MO_64, 56);
TRANS(VEXTSH2D, do_vexts, MO_64, 48);
TRANS(VEXTSW2D, do_vexts, MO_64, 32);
+static bool trans_VEXTSD2Q(DisasContext *ctx, arg_VX_tb *a)
+{
+ TCGv_i64 tmp;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tmp = tcg_temp_new_i64();
+
+ get_avr64(tmp, a->vrb, false);
+ set_avr64(a->vrt, tmp, false);
+ tcg_gen_sari_i64(tmp, tmp, 63);
+ set_avr64(a->vrt, tmp, true);
+
+ tcg_temp_free_i64(tmp);
+ return true;
+}
+
GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
--
2.25.1
- [PATCH 00/37] target/ppc: PowerISA Vector/VSX instruction batch, matheus . ferst, 2022/01/07
- [PATCH 01/37] target/ppc: Introduce TRANS*FLAGS macros, matheus . ferst, 2022/01/07
- [PATCH 03/37] target/ppc: Moved vector multiply high and low to decodetree, matheus . ferst, 2022/01/07
- [PATCH 02/37] target/ppc: moved vector even and odd multiplication to decodetree, matheus . ferst, 2022/01/07
- [PATCH 04/37] target/ppc: vmulh* instructions use gvec, matheus . ferst, 2022/01/07
- [PATCH 05/37] target/ppc: Implement vmsumcud instruction, matheus . ferst, 2022/01/07
- [PATCH 06/37] target/ppc: Implement vmsumudm instruction, matheus . ferst, 2022/01/07
- [PATCH 07/37] target/ppc: Move vexts[bhw]2[wd] to decodetree, matheus . ferst, 2022/01/07
- [PATCH 08/37] target/ppc: Implement vextsd2q,
matheus . ferst <=
- [PATCH 09/37] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree, matheus . ferst, 2022/01/07
- [PATCH 10/37] target/ppc: Move Vector Compare Not Equal or Zero to decodetree, matheus . ferst, 2022/01/07
- [PATCH 12/37] target/ppc: Implement Vector Compare Greater Than Quadword, matheus . ferst, 2022/01/07
- [PATCH 11/37] target/ppc: Implement Vector Compare Equal Quadword, matheus . ferst, 2022/01/07
- [PATCH 13/37] target/ppc: Implement Vector Compare Quadword, matheus . ferst, 2022/01/07
- [PATCH 14/37] target/ppc: implement vstri[bh][lr], matheus . ferst, 2022/01/07
- [PATCH 15/37] target/ppc: implement vclrlb, matheus . ferst, 2022/01/07
- [PATCH 16/37] target/ppc: implement vclrrb, matheus . ferst, 2022/01/07
- [PATCH 17/37] target/ppc: implement vcntmb[bhwd], matheus . ferst, 2022/01/07
- [PATCH 19/37] target/ppc: Move vsel and vperm/vpermr to decodetree, matheus . ferst, 2022/01/07