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[PULL 14/48] target/ppc: moved ppc_store_sdr1 to cpu.c
From: |
David Gibson |
Subject: |
[PULL 14/48] target/ppc: moved ppc_store_sdr1 to cpu.c |
Date: |
Wed, 19 May 2021 22:51:14 +1000 |
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
Moved this function that is required in !TCG cases into a
common code file
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Message-Id: <20210512140813.112884-3-bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[dwg: Fixed compile error with linux-user targets]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.c | 31 +++++++++++++++++++++++++++++++
target/ppc/mmu_helper.c | 26 --------------------------
2 files changed, 31 insertions(+), 26 deletions(-)
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index cb794e9f4f..d957d1a687 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -20,7 +20,10 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "cpu-models.h"
+#include "cpu-qom.h"
+#include "exec/log.h"
#include "fpu/softfloat-helpers.h"
+#include "mmu-hash64.h"
target_ulong cpu_read_xer(CPUPPCState *env)
{
@@ -61,3 +64,31 @@ uint32_t ppc_get_vscr(CPUPPCState *env)
uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0;
return env->vscr | (sat << VSCR_SAT);
}
+
+#ifdef CONFIG_SOFTMMU
+void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
+ assert(!cpu->vhyp);
+#if defined(TARGET_PPC64)
+ if (mmu_is_64bit(env->mmu_model)) {
+ target_ulong sdr_mask = SDR_64_HTABORG | SDR_64_HTABSIZE;
+ target_ulong htabsize = value & SDR_64_HTABSIZE;
+
+ if (value & ~sdr_mask) {
+ error_report("Invalid bits 0x"TARGET_FMT_lx" set in SDR1",
+ value & ~sdr_mask);
+ value &= sdr_mask;
+ }
+ if (htabsize > 28) {
+ error_report("Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
+ htabsize);
+ return;
+ }
+ }
+#endif /* defined(TARGET_PPC64) */
+ /* FIXME: Should check for valid HTABMASK values in 32-bit case */
+ env->spr[SPR_SDR1] = value;
+}
+#endif /* CONFIG_SOFTMMU */
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index ca88658cba..06e1ebdcbc 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -2085,32 +2085,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
target_ulong addr)
/*****************************************************************************/
/* Special registers manipulation */
-void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
-{
- PowerPCCPU *cpu = env_archcpu(env);
- qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
- assert(!cpu->vhyp);
-#if defined(TARGET_PPC64)
- if (mmu_is_64bit(env->mmu_model)) {
- target_ulong sdr_mask = SDR_64_HTABORG | SDR_64_HTABSIZE;
- target_ulong htabsize = value & SDR_64_HTABSIZE;
-
- if (value & ~sdr_mask) {
- error_report("Invalid bits 0x"TARGET_FMT_lx" set in SDR1",
- value & ~sdr_mask);
- value &= sdr_mask;
- }
- if (htabsize > 28) {
- error_report("Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
- htabsize);
- return;
- }
- }
-#endif /* defined(TARGET_PPC64) */
- /* FIXME: Should check for valid HTABMASK values in 32-bit case */
- env->spr[SPR_SDR1] = value;
-}
-
#if defined(TARGET_PPC64)
void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
{
--
2.31.1
- [PULL 02/48] hw/ppc/spapr.c: Make sure the host supports the selected MMU mode, (continued)
- [PULL 02/48] hw/ppc/spapr.c: Make sure the host supports the selected MMU mode, David Gibson, 2021/05/19
- [PULL 01/48] hw/ppc/spapr.c: Extract MMU mode error reporting into a function, David Gibson, 2021/05/19
- [PULL 04/48] target/ppc: renamed SPR registration functions, David Gibson, 2021/05/19
- [PULL 08/48] target/ppc: moved ppc_store_lpcr to misc_helper.c, David Gibson, 2021/05/19
- [PULL 09/48] hw/ppc: moved has_spr to cpu.h, David Gibson, 2021/05/19
- [PULL 10/48] target/ppc: turned SPR R/W callbacks not static, David Gibson, 2021/05/19
- [PULL 11/48] target/ppc: isolated cpu init from translation logic, David Gibson, 2021/05/19
- [PULL 07/48] target/ppc: moved function out of mmu-hash64, David Gibson, 2021/05/19
- [PULL 16/48] target/ppc: Add cia field to DisasContext, David Gibson, 2021/05/19
- [PULL 17/48] target/ppc: Split out decode_legacy, David Gibson, 2021/05/19
- [PULL 14/48] target/ppc: moved ppc_store_sdr1 to cpu.c,
David Gibson <=
- [PULL 20/48] target/ppc: Remove special case for POWERPC_EXCP_TRAP, David Gibson, 2021/05/19
- [PULL 18/48] target/ppc: Move DISAS_NORETURN setting into gen_exception*, David Gibson, 2021/05/19
- [PULL 22/48] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE}, David Gibson, 2021/05/19
- [PULL 06/48] hw/ppc: moved hcalls that depend on softmmu, David Gibson, 2021/05/19
- [PULL 12/48] target/ppc: created ppc_{store, get}_vscr for generic vscr usage, David Gibson, 2021/05/19
- [PULL 05/48] target/ppc: move SPR R/W callbacks to translate.c, David Gibson, 2021/05/19
- [PULL 28/48] target/ppc: Remove DisasContext.exception, David Gibson, 2021/05/19
- [PULL 13/48] target/ppc: updated vscr manipulation in machine.c, David Gibson, 2021/05/19
- [PULL 15/48] target/ppc: moved ppc_cpu_dump_state to cpu_init.c, David Gibson, 2021/05/19
- [PULL 19/48] target/ppc: Remove special case for POWERPC_SYSCALL, David Gibson, 2021/05/19