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[PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags
From: |
David Gibson |
Subject: |
[PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags |
Date: |
Tue, 4 May 2021 15:52:39 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
Because these bits were not in hflags, the code generated
for single-stepping on BookE was essentially random.
Recompute hflags when storing to dbcr0.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-5-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper_regs.c | 24 +++++++++++++++++-------
target/ppc/misc_helper.c | 3 +++
target/ppc/translate.c | 11 -----------
3 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index df9673b90f..e345966b6b 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -114,13 +114,23 @@ void hreg_compute_hflags(CPUPPCState *env)
hflags |= le << MSR_LE;
}
- if (ppc_flags & POWERPC_FLAG_BE) {
- QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
- msr_mask |= 1 << MSR_BE;
- }
- if (ppc_flags & POWERPC_FLAG_SE) {
- QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
- msr_mask |= 1 << MSR_SE;
+ if (ppc_flags & POWERPC_FLAG_DE) {
+ target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
+ if (dbcr0 & DBCR0_ICMP) {
+ hflags |= 1 << HFLAGS_SE;
+ }
+ if (dbcr0 & DBCR0_BRT) {
+ hflags |= 1 << HFLAGS_BE;
+ }
+ } else {
+ if (ppc_flags & POWERPC_FLAG_BE) {
+ QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
+ msr_mask |= 1 << MSR_BE;
+ }
+ if (ppc_flags & POWERPC_FLAG_SE) {
+ QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
+ msr_mask |= 1 << MSR_SE;
+ }
}
if (msr_is_64bit(env, msr)) {
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index b04b4d7c6e..002958be26 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -215,6 +215,9 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num,
target_ulong value)
void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
{
+ /* Bits 26 & 27 affect single-stepping. */
+ hreg_compute_hflags(env);
+ /* Bits 28 & 29 affect reset or shutdown. */
store_40x_dbcr0(env, val);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a85b890bb0..7912495f28 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7923,17 +7923,6 @@ static void ppc_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
if ((hflags >> HFLAGS_BE) & 1) {
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
}
- if ((env->flags & POWERPC_FLAG_DE) && msr_de) {
- ctx->singlestep_enabled = 0;
- target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
- if (dbcr0 & DBCR0_ICMP) {
- ctx->singlestep_enabled |= CPU_SINGLE_STEP;
- }
- if (dbcr0 & DBCR0_BRT) {
- ctx->singlestep_enabled |= CPU_BRANCH_STEP;
- }
-
- }
if (unlikely(ctx->base.singlestep_enabled)) {
ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
}
--
2.31.1
- [PULL 07/46] target/ppc: Fix comment for MSR_FE{0,1}, (continued)
- [PULL 07/46] target/ppc: Fix comment for MSR_FE{0,1}, David Gibson, 2021/05/04
- [PULL 09/46] hw/ppc/spapr_rtas: Update hflags after setting msr, David Gibson, 2021/05/04
- [PULL 10/46] target/ppc: Extract post_load_update_msr, David Gibson, 2021/05/04
- [PULL 11/46] target/ppc: Disconnect hflags from MSR, David Gibson, 2021/05/04
- [PULL 14/46] target/ppc: Create helper_scv, David Gibson, 2021/05/04
- [PULL 15/46] target/ppc: Put LPCR[GTSE] in hflags, David Gibson, 2021/05/04
- [PULL 12/46] target/ppc: Reduce env->hflags to uint32_t, David Gibson, 2021/05/04
- [PULL 17/46] target/ppc: Remove env->immu_idx and env->dmmu_idx, David Gibson, 2021/05/04
- [PULL 19/46] target/ppc: Validate hflags with CONFIG_DEBUG_TCG, David Gibson, 2021/05/04
- [PULL 16/46] target/ppc: Remove MSR_SA and MSR_AP from hflags, David Gibson, 2021/05/04
- [PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags,
David Gibson <=
- [PULL 18/46] linux-user/ppc: Fix msr updates for signal handling, David Gibson, 2021/05/04
- [PULL 20/46] vt82c686: QOM-ify superio related functionality, David Gibson, 2021/05/04
- [PULL 25/46] hw/ppc: Add emulation of Genesi/bPlan Pegasos II, David Gibson, 2021/05/04
- [PULL 24/46] hw/pci-host: Add emulation of Marvell MV64361 PPC system controller, David Gibson, 2021/05/04
- [PULL 21/46] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO, David Gibson, 2021/05/04
- [PULL 22/46] vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it, David Gibson, 2021/05/04
- [PULL 26/46] spapr: Rename RTAS_MAX_ADDR to FDT_MAX_ADDR, David Gibson, 2021/05/04
- [PULL 23/46] vt82c686: Add emulation of VT8231 south bridge, David Gibson, 2021/05/04
- [PULL 27/46] ppc/spapr: Add support for implement support for H_SCM_HEALTH, David Gibson, 2021/05/04
- [PULL 31/46] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour, David Gibson, 2021/05/04