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[PULL 07/46] target/ppc: Fix comment for MSR_FE{0,1}
From: |
David Gibson |
Subject: |
[PULL 07/46] target/ppc: Fix comment for MSR_FE{0,1} |
Date: |
Tue, 4 May 2021 15:52:33 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
As per hreg_compute_hflags:
We 'forget' FE0 & FE1: we'll never generate imprecise exceptions
remove the hflags marker from the respective comments.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-7-richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 79c4033a42..fd13489dce 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -322,13 +322,13 @@ typedef struct ppc_v3_pate_t {
#define MSR_PR 14 /* Problem state hflags */
#define MSR_FP 13 /* Floating point available hflags */
#define MSR_ME 12 /* Machine check interrupt enable */
-#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
+#define MSR_FE0 11 /* Floating point exception mode 0 */
#define MSR_SE 10 /* Single-step trace enable x hflags */
#define MSR_DWE 10 /* Debug wait enable on 405 x */
#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
#define MSR_BE 9 /* Branch trace enable x hflags */
#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
-#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
+#define MSR_FE1 8 /* Floating point exception mode 1 */
#define MSR_AL 7 /* AL bit on POWER */
#define MSR_EP 6 /* Exception prefix on 601 */
#define MSR_IR 5 /* Instruction relocate */
--
2.31.1
- [PULL 00/46] ppc-for-6.1 queue 20210504, David Gibson, 2021/05/04
- [PULL 01/46] hw/ppc/mac_newworld: Restrict RAM to 2 GiB, David Gibson, 2021/05/04
- [PULL 03/46] target/ppc: Move 601 hflags adjustment to hreg_compute_hflags, David Gibson, 2021/05/04
- [PULL 02/46] target/ppc: Move helper_regs.h functions out-of-line, David Gibson, 2021/05/04
- [PULL 04/46] target/ppc: Properly sync cpu state with new msr in cpu_load_old, David Gibson, 2021/05/04
- [PULL 08/46] hw/ppc/pnv_core: Update hflags after setting msr, David Gibson, 2021/05/04
- [PULL 05/46] target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr, David Gibson, 2021/05/04
- [PULL 06/46] target/ppc: Retain hflags_nmsr only for migration, David Gibson, 2021/05/04
- [PULL 07/46] target/ppc: Fix comment for MSR_FE{0,1},
David Gibson <=
- [PULL 09/46] hw/ppc/spapr_rtas: Update hflags after setting msr, David Gibson, 2021/05/04
- [PULL 10/46] target/ppc: Extract post_load_update_msr, David Gibson, 2021/05/04
- [PULL 11/46] target/ppc: Disconnect hflags from MSR, David Gibson, 2021/05/04
- [PULL 14/46] target/ppc: Create helper_scv, David Gibson, 2021/05/04
- [PULL 15/46] target/ppc: Put LPCR[GTSE] in hflags, David Gibson, 2021/05/04
- [PULL 12/46] target/ppc: Reduce env->hflags to uint32_t, David Gibson, 2021/05/04
- [PULL 17/46] target/ppc: Remove env->immu_idx and env->dmmu_idx, David Gibson, 2021/05/04
- [PULL 19/46] target/ppc: Validate hflags with CONFIG_DEBUG_TCG, David Gibson, 2021/05/04
- [PULL 16/46] target/ppc: Remove MSR_SA and MSR_AP from hflags, David Gibson, 2021/05/04
- [PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags, David Gibson, 2021/05/04