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[PULL 15/46] target/ppc: Put LPCR[GTSE] in hflags
From: |
David Gibson |
Subject: |
[PULL 15/46] target/ppc: Put LPCR[GTSE] in hflags |
Date: |
Tue, 4 May 2021 15:52:41 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
Because this bit was not in hflags, the privilege check
for tlb instructions was essentially random.
Recompute hflags when storing to LPCR.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-7-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 1 +
target/ppc/helper_regs.c | 3 +++
target/ppc/mmu-hash64.c | 3 +++
target/ppc/translate.c | 2 +-
4 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d5f362506a..3c28ddb331 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -596,6 +596,7 @@ enum {
HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */
HFLAGS_HV = 1, /* computed from MSR_HV and other state */
HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
+ HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
HFLAGS_DR = 4, /* MSR_DR */
HFLAGS_IR = 5, /* MSR_IR */
HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index e345966b6b..f85bb14d1d 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -149,6 +149,9 @@ void hreg_compute_hflags(CPUPPCState *env)
if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
hflags |= 1 << HFLAGS_TM;
}
+ if (env->spr[SPR_LPCR] & LPCR_GTSE) {
+ hflags |= 1 << HFLAGS_GTSE;
+ }
#ifndef CONFIG_USER_ONLY
if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 0fabc10302..d517a99832 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -30,6 +30,7 @@
#include "exec/log.h"
#include "hw/hw.h"
#include "mmu-book3s-v3.h"
+#include "helper_regs.h"
/* #define DEBUG_SLB */
@@ -1125,6 +1126,8 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
CPUPPCState *env = &cpu->env;
env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
+ /* The gtse bit affects hflags */
+ hreg_compute_hflags(env);
}
void helper_store_lpcr(CPUPPCState *env, target_ulong val)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d48c554290..5e629291d3 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7908,7 +7908,7 @@ static void ppc_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
- ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
+ ctx->gtse = (hflags >> HFLAGS_GTSE) & 1;
ctx->singlestep_enabled = 0;
if ((hflags >> HFLAGS_SE) & 1) {
--
2.31.1
- [PULL 02/46] target/ppc: Move helper_regs.h functions out-of-line, (continued)
- [PULL 02/46] target/ppc: Move helper_regs.h functions out-of-line, David Gibson, 2021/05/04
- [PULL 04/46] target/ppc: Properly sync cpu state with new msr in cpu_load_old, David Gibson, 2021/05/04
- [PULL 08/46] hw/ppc/pnv_core: Update hflags after setting msr, David Gibson, 2021/05/04
- [PULL 05/46] target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr, David Gibson, 2021/05/04
- [PULL 06/46] target/ppc: Retain hflags_nmsr only for migration, David Gibson, 2021/05/04
- [PULL 07/46] target/ppc: Fix comment for MSR_FE{0,1}, David Gibson, 2021/05/04
- [PULL 09/46] hw/ppc/spapr_rtas: Update hflags after setting msr, David Gibson, 2021/05/04
- [PULL 10/46] target/ppc: Extract post_load_update_msr, David Gibson, 2021/05/04
- [PULL 11/46] target/ppc: Disconnect hflags from MSR, David Gibson, 2021/05/04
- [PULL 14/46] target/ppc: Create helper_scv, David Gibson, 2021/05/04
- [PULL 15/46] target/ppc: Put LPCR[GTSE] in hflags,
David Gibson <=
- [PULL 12/46] target/ppc: Reduce env->hflags to uint32_t, David Gibson, 2021/05/04
- [PULL 17/46] target/ppc: Remove env->immu_idx and env->dmmu_idx, David Gibson, 2021/05/04
- [PULL 19/46] target/ppc: Validate hflags with CONFIG_DEBUG_TCG, David Gibson, 2021/05/04
- [PULL 16/46] target/ppc: Remove MSR_SA and MSR_AP from hflags, David Gibson, 2021/05/04
- [PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags, David Gibson, 2021/05/04
- [PULL 18/46] linux-user/ppc: Fix msr updates for signal handling, David Gibson, 2021/05/04
- [PULL 20/46] vt82c686: QOM-ify superio related functionality, David Gibson, 2021/05/04
- [PULL 25/46] hw/ppc: Add emulation of Genesi/bPlan Pegasos II, David Gibson, 2021/05/04
- [PULL 24/46] hw/pci-host: Add emulation of Marvell MV64361 PPC system controller, David Gibson, 2021/05/04
- [PULL 21/46] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO, David Gibson, 2021/05/04