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Re: [PATCH v2 11/15] target/ppc: Move D/DS/X-form integer loads to decod
From: |
Matheus K. Ferst |
Subject: |
Re: [PATCH v2 11/15] target/ppc: Move D/DS/X-form integer loads to decodetree |
Date: |
Wed, 28 Apr 2021 10:31:19 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 |
On 27/04/2021 14:16, Luis Pires wrote:
From: Richard Henderson <richard.henderson@linaro.org>
These are all connected by macros in the legacy decoding.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 37 ++++
target/ppc/translate.c | 136 ++-------------
target/ppc/translate/fixedpoint-impl.c.inc | 188 +++++++++++++++++++++
3 files changed, 238 insertions(+), 123 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 878d2f2f66..bf39ce5c15 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -20,6 +20,43 @@
&D rt ra si
@D ...... rt:5 ra:5 si:s16 &D
+%ds_si 2:s14 !function=times_4
+@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+
+&X rt ra rb
+@X ...... rt:5 ra:5 rb:5 .......... . &X
+
This is a bit problematic, the instruction form isn't enough to decide its
fields. Eg. setb is X-form, but the fields are rt:5 bfa:3, setbc is also
X-form
and the fields are rt:5 ba:5. In fact, for the X-form, there is a whole
page of
field designations in PowerISA v3.1.
I would break this into three cases:
- Some forms have single field designations. Eg. B, XLS, XX4;
- Others have multiple designations but are just alternative names for the
fields. Eg. DQ, DS, M;
- And there are forms with multiple designations, with a variable
number of
fields that may overlap each other. Eg. X, XFX, XX2.
The first is a non-issue, just use the form name as done here. The
second seems
tractable, we could pick one field name for each part of the insn and
still use
the form name as the identifier for args_def/fmt_def. The last case will
likely
require multiple fmt_defs for each form, in which case we would need to
come up
with a pattern to name them.
Looking at what Binutils did when they added Power10 support, it seems
that the
insn form is just a hint for opcode positions, and fields are specified
for each
insn. The sad part of this kind of approach is that it would leave us
with, eg.
arg_LBZX and arg_LBZUX instead of a single arg_X, making it harder to put
multiple insns under the same implementation.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software JĂșnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
- Re: [PATCH v2 04/15] target/ppc: Move DISAS_NORETURN setting into gen_exception*, (continued)
- [PATCH v2 05/15] target/ppc: Tidy exception vs exit_tb, Luis Pires, 2021/04/27
- [PATCH v2 06/15] target/ppc: Mark helper_raise_exception* as noreturn, Luis Pires, 2021/04/27
- [PATCH v2 07/15] target/ppc: Use translator_loop_temp_check, Luis Pires, 2021/04/27
- [PATCH v2 08/15] target/ppc: Add infrastructure for prefixed insns, Luis Pires, 2021/04/27
- [PATCH v2 09/15] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI, Luis Pires, 2021/04/27
- [PATCH v2 10/15] target/ppc: Implement PNOP, Luis Pires, 2021/04/27
- [PATCH v2 11/15] target/ppc: Move D/DS/X-form integer loads to decodetree, Luis Pires, 2021/04/27
- Re: [PATCH v2 11/15] target/ppc: Move D/DS/X-form integer loads to decodetree,
Matheus K. Ferst <=
- [PATCH v2 12/15] target/ppc: Implement prefixed integer load instructions, Luis Pires, 2021/04/27
- [PATCH v2 13/15] target/ppc: Move D/DS/X-form integer stores to decodetree, Luis Pires, 2021/04/27
- [PATCH v2 14/15] target/ppc: Implement prefixed integer store instructions, Luis Pires, 2021/04/27
- [PATCH v2 15/15] target/ppc: Check cpu flags for prefixed insn support, Luis Pires, 2021/04/27