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[PULL 16/88] ppc/pnv: Add a LPC "ranges" property
From: |
David Gibson |
Subject: |
[PULL 16/88] ppc/pnv: Add a LPC "ranges" property |
Date: |
Tue, 17 Dec 2019 15:42:10 +1100 |
From: Cédric Le Goater <address@hidden>
And fix a typo in the MEM address space definition.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv_lpc.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index fb9f930320..c5a85c38c7 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -86,7 +86,7 @@ enum {
#define ISA_FW_SIZE 0x10000000
#define LPC_IO_OPB_ADDR 0xd0010000
#define LPC_IO_OPB_SIZE 0x00010000
-#define LPC_MEM_OPB_ADDR 0xe0010000
+#define LPC_MEM_OPB_ADDR 0xe0000000
#define LPC_MEM_OPB_SIZE 0x10000000
#define LPC_FW_OPB_ADDR 0xf0000000
#define LPC_FW_OPB_SIZE 0x10000000
@@ -143,6 +143,16 @@ int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
cpu_to_be32(PNV9_LPCM_SIZE >> 32),
cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
};
+ uint32_t lpc_ranges[12] = { 0, 0,
+ cpu_to_be32(LPC_MEM_OPB_ADDR),
+ cpu_to_be32(LPC_MEM_OPB_SIZE),
+ cpu_to_be32(1), 0,
+ cpu_to_be32(LPC_IO_OPB_ADDR),
+ cpu_to_be32(LPC_IO_OPB_SIZE),
+ cpu_to_be32(3), 0,
+ cpu_to_be32(LPC_FW_OPB_ADDR),
+ cpu_to_be32(LPC_FW_OPB_SIZE),
+ };
uint32_t reg[2];
/*
@@ -211,6 +221,8 @@ int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
_FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat,
sizeof(lpc_compat))));
+ _FDT((fdt_setprop(fdt, offset, "ranges", lpc_ranges,
+ sizeof(lpc_ranges))));
return 0;
}
--
2.23.0
- [PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer, (continued)
- [PULL 06/88] xive: Link "xive" property to XiveEndSource::xrtr pointer, David Gibson, 2019/12/16
- [PULL 11/88] ppc/pnv: Link "chip" property to PnvXive::chip pointer, David Gibson, 2019/12/16
- [PULL 10/88] ppc/pnv: Link "chip" property to PnvCore::chip pointer, David Gibson, 2019/12/16
- [PULL 09/88] ppc/pnv: Link "chip" property to PnvHomer::chip pointer, David Gibson, 2019/12/16
- [PULL 07/88] ppc/pnv: Link "psi" property to PnvLpc::psi pointer, David Gibson, 2019/12/16
- [PULL 08/88] ppc/pnv: Link "psi" property to PnvOCC::psi pointer, David Gibson, 2019/12/16
- [PULL 19/88] ppc/pnv: Remove pnv_xive_vst_size() routine, David Gibson, 2019/12/16
- [PULL 15/88] spapr: Abort if XICS interrupt controller cannot be initialized, David Gibson, 2019/12/16
- [PULL 20/88] xive/kvm: Trigger interrupts from userspace, David Gibson, 2019/12/16
- [PULL 18/88] ppc/xive: Introduce helpers for the NVT id, David Gibson, 2019/12/16
- [PULL 16/88] ppc/pnv: Add a LPC "ranges" property,
David Gibson <=
- [PULL 14/88] xics: Link ICP_PROP_CPU property to ICPState::cs pointer, David Gibson, 2019/12/16
- [PULL 23/88] ppc/xive: Check V bit in TM_PULL_POOL_CTX, David Gibson, 2019/12/16
- [PULL 13/88] xics: Link ICP_PROP_XICS property to ICPState::xics pointer, David Gibson, 2019/12/16
- [PULL 17/88] ppc/xive: Record the IPB in the associated NVT, David Gibson, 2019/12/16
- [PULL 27/88] ppc/xive: Introduce a XivePresenter interface, David Gibson, 2019/12/16
- [PULL 26/88] ppc/pnv: Create BMC devices at machine init, David Gibson, 2019/12/16
- [PULL 28/88] ppc/xive: Implement the XivePresenter interface, David Gibson, 2019/12/16
- [PULL 21/88] ppc/pnv: Quiesce some XIVE errors, David Gibson, 2019/12/16
- [PULL 22/88] ppc/xive: Introduce OS CAM line helpers, David Gibson, 2019/12/16
- [PULL 24/88] ipmi: Add support to customize OEM functions, David Gibson, 2019/12/16