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[Qemu-ppc] [PATCH 7/8] target/ppc: introduce vsrh_offset() function
From: |
Mark Cave-Ayland |
Subject: |
[Qemu-ppc] [PATCH 7/8] target/ppc: introduce vsrh_offset() function |
Date: |
Sun, 3 Mar 2019 17:23:42 +0000 |
Now that both VSX and VMX registers are in host-endian order we can introduce
a vsrh_offset() function as a replacement for fpr_offset().
In addition the avrh_offset() and avrl_offset() functions can be simplified in
terms of vsrh_offset() and vsrl_offset().
Signed-off-by: Mark Cave-Ayland <address@hidden>
---
target/ppc/cpu.h | 16 ++++++++--------
target/ppc/translate.c | 4 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index faae25a566..9f8eb0bdc0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2583,16 +2583,11 @@ static inline bool lsw_reg_in_range(int start, int
nregs, int rx)
#define VsrSD(i) s64[1 - (i)]
#endif
-static inline int fpr_offset(int i)
+static inline int vsrh_offset(int i)
{
return offsetof(CPUPPCState, vsr[i].VsrD(0));
}
-static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
-{
- return (uint64_t *)((uintptr_t)env + fpr_offset(i));
-}
-
static inline int vsrl_offset(int i)
{
return offsetof(CPUPPCState, vsr[i].VsrD(1));
@@ -2603,6 +2598,11 @@ static inline int vsr_full_offset(int i)
return offsetof(CPUPPCState, vsr[i].u64[0]);
}
+static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
+{
+ return (uint64_t *)((uintptr_t)env + vsrh_offset(i));
+}
+
static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
{
return (uint64_t *)((uintptr_t)env + vsrl_offset(i));
@@ -2610,12 +2610,12 @@ static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env,
int i)
static inline int avrh_offset(int i)
{
- return offsetof(CPUPPCState, vsr[32 + i].VsrD(0));
+ return vsrh_offset(i + 32);
}
static inline int avrl_offset(int i)
{
- return offsetof(CPUPPCState, vsr[32 + i].VsrD(1));
+ return vsrl_offset(i + 32);
}
static inline int avr_offset(int i)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f646f359e7..1c7377d588 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6677,12 +6677,12 @@ GEN_TM_PRIV_NOOP(trechkpt);
static inline void get_fpr(TCGv_i64 dst, int regno)
{
- tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
+ tcg_gen_ld_i64(dst, cpu_env, vsrh_offset(regno));
}
static inline void set_fpr(int regno, TCGv_i64 src)
{
- tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
+ tcg_gen_st_i64(src, cpu_env, vsrh_offset(regno));
}
static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
--
2.11.0
- [Qemu-ppc] [PATCH 3/8] target/ppc: move Vsr* macros from internal.h to cpu.h, (continued)
[Qemu-ppc] [PATCH 5/8] target/ppc: introduce avr_offset() function, Mark Cave-Ayland, 2019/03/03
[Qemu-ppc] [PATCH 7/8] target/ppc: introduce vsrh_offset() function,
Mark Cave-Ayland <=
[Qemu-ppc] [PATCH 2/8] target/ppc: introduce single vsrl_offset() function, Mark Cave-Ayland, 2019/03/03
[Qemu-ppc] [PATCH 4/8] target/ppc: introduce avrh_offset() and avrl_offset() functions, Mark Cave-Ayland, 2019/03/03
[Qemu-ppc] [PATCH 6/8] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, Mark Cave-Ayland, 2019/03/03