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[Qemu-ppc] [PATCH 09/17] ppc: reorganize gen_compute_fprf
From: |
Paolo Bonzini |
Subject: |
[Qemu-ppc] [PATCH 09/17] ppc: reorganize gen_compute_fprf |
Date: |
Thu, 28 Aug 2014 19:15:05 +0200 |
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-ppc/translate.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0a85a23..afbd336 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -253,21 +253,19 @@ static inline void gen_compute_fprf(TCGv_i64 arg, int
set_fprf, int set_rc)
{
TCGv_i32 t0 = tcg_temp_new_i32();
- if (set_fprf != 0) {
- /* This case might be optimized later */
- tcg_gen_movi_i32(t0, 1);
- gen_helper_compute_fprf(t0, cpu_env, arg, t0);
- if (unlikely(set_rc)) {
- tcg_gen_mov_i32(cpu_crf[1], t0);
- }
- gen_helper_float_check_status(cpu_env);
- } else if (unlikely(set_rc)) {
- /* We always need to compute fpcc */
- tcg_gen_movi_i32(t0, 0);
- gen_helper_compute_fprf(t0, cpu_env, arg, t0);
+ if (set_fprf == 0 && !set_rc) {
+ return;
+ }
+
+ tcg_gen_movi_i32(t0, set_fprf != 0);
+ gen_helper_compute_fprf(t0, cpu_env, arg, t0);
+ if (set_rc) {
tcg_gen_mov_i32(cpu_crf[1], t0);
}
+ if (set_fprf != 0) {
+ gen_helper_float_check_status(cpu_env);
+ }
tcg_temp_free_i32(t0);
}
--
1.8.3.1
- [Qemu-ppc] [PATCH 01/17] ppc: do not look at the MMU index, (continued)
- [Qemu-ppc] [PATCH 01/17] ppc: do not look at the MMU index, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 02/17] ppc: avoid excessive TLB flushing, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 04/17] ppc: use ARRAY_SIZE in gdbstub.c, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 03/17] ppc: fix monitor access to CR, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 05/17] ppc: use CRF_* in fpu_helper.c, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 06/17] ppc: use CRF_* in int_helper.c, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 07/17] ppc: fix result of DLMZB when no zero bytes are found, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 08/17] ppc: introduce helpers for mfocrf/mtocrf, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 09/17] ppc: reorganize gen_compute_fprf,
Paolo Bonzini <=
- [Qemu-ppc] [PATCH 10/17] ppc: introduce gen_op_mfcr/gen_op_mtcr, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 11/17] ppc: rename gen_set_cr6_from_fpscr, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 14/17] ppc: introduce ppc_get_crf and ppc_set_crf, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 13/17] ppc: compute mask from BI using right shift, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 15/17] ppc: store CR registers in 32 1-bit registers, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 16/17] ppc: inline ppc_get_crf/ppc_set_crf when clearer, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 17/17] ppc: dump all 32 CR bits, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 12/17] ppc: use movcond for isel, Paolo Bonzini, 2014/08/28
- Re: [Qemu-ppc] [RFT/RFH PATCH 00/16] PPC speedup patches for TCG, Tom Musta, 2014/08/28