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[Qemu-ppc] [PATCH 05/17] ppc: use CRF_* in fpu_helper.c
From: |
Paolo Bonzini |
Subject: |
[Qemu-ppc] [PATCH 05/17] ppc: use CRF_* in fpu_helper.c |
Date: |
Thu, 28 Aug 2014 19:15:01 +0200 |
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-ppc/fpu_helper.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index da93d12..0fe006a 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1043,7 +1043,7 @@ uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
}
}
- return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
+ return (1 << CRF_LT) | (fg_flag << CRF_GT) | (fe_flag << CRF_EQ);
}
uint32_t helper_ftsqrt(uint64_t frb)
@@ -1074,7 +1074,7 @@ uint32_t helper_ftsqrt(uint64_t frb)
}
}
- return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
+ return (1 << CRF_LT) | (fg_flag << CRF_GT) | (fe_flag << CRF_EQ);
}
void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
@@ -1088,19 +1088,19 @@ void helper_fcmpu(CPUPPCState *env, uint64_t arg1,
uint64_t arg2,
if (unlikely(float64_is_any_nan(farg1.d) ||
float64_is_any_nan(farg2.d))) {
- ret = 0x01UL;
+ ret = CRF_SO;
} else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
- ret = 0x08UL;
+ ret = CRF_LT;
} else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
- ret = 0x04UL;
+ ret = CRF_GT;
} else {
- ret = 0x02UL;
+ ret = CRF_EQ;
}
env->fpscr &= ~(0x0F << FPSCR_FPRF);
- env->fpscr |= ret << FPSCR_FPRF;
- env->crf[crfD] = ret;
- if (unlikely(ret == 0x01UL
+ env->fpscr |= (0x01 << FPSCR_FPRF) << ret;
+ env->crf[crfD] = (1 << ret);
+ if (unlikely(ret == CRF_SO
&& (float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d)))) {
/* sNaN comparison */
@@ -1119,19 +1119,19 @@ void helper_fcmpo(CPUPPCState *env, uint64_t arg1,
uint64_t arg2,
if (unlikely(float64_is_any_nan(farg1.d) ||
float64_is_any_nan(farg2.d))) {
- ret = 0x01UL;
+ ret = CRF_SO;
} else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
- ret = 0x08UL;
+ ret = CRF_LT;
} else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
- ret = 0x04UL;
+ ret = CRF_GT;
} else {
- ret = 0x02UL;
+ ret = CRF_EQ;
}
env->fpscr &= ~(0x0F << FPSCR_FPRF);
- env->fpscr |= ret << FPSCR_FPRF;
- env->crf[crfD] = ret;
- if (unlikely(ret == 0x01UL)) {
+ env->fpscr |= (0x01 << FPSCR_FPRF) << ret;
+ env->crf[crfD] = (1 << ret);
+ if (unlikely(ret == CRF_SO)) {
if (float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d)) {
/* sNaN comparison */
--
1.8.3.1
- [Qemu-ppc] [RFT/RFH PATCH 00/16] PPC speedup patches for TCG, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 01/17] ppc: do not look at the MMU index, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 02/17] ppc: avoid excessive TLB flushing, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 04/17] ppc: use ARRAY_SIZE in gdbstub.c, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 03/17] ppc: fix monitor access to CR, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 05/17] ppc: use CRF_* in fpu_helper.c,
Paolo Bonzini <=
- [Qemu-ppc] [PATCH 06/17] ppc: use CRF_* in int_helper.c, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 07/17] ppc: fix result of DLMZB when no zero bytes are found, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 08/17] ppc: introduce helpers for mfocrf/mtocrf, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 09/17] ppc: reorganize gen_compute_fprf, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 10/17] ppc: introduce gen_op_mfcr/gen_op_mtcr, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 11/17] ppc: rename gen_set_cr6_from_fpscr, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 14/17] ppc: introduce ppc_get_crf and ppc_set_crf, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 13/17] ppc: compute mask from BI using right shift, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 15/17] ppc: store CR registers in 32 1-bit registers, Paolo Bonzini, 2014/08/28
- [Qemu-ppc] [PATCH 16/17] ppc: inline ppc_get_crf/ppc_set_crf when clearer, Paolo Bonzini, 2014/08/28