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[Qemu-ppc] [PATCH 30/48] mmu-hash*: Fold pte_check*() logic into caller
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PATCH 30/48] mmu-hash*: Fold pte_check*() logic into caller |
Date: |
Tue, 12 Mar 2013 21:31:32 +1100 |
With previous cleanups made, the 32-bit and 64-bit pte_check*() functions
are pretty trivial and only have one call site. This patch therefore
clarifies the overall code flow by folding those functions into their
call site.
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/mmu-hash32.c | 48 +++++++++++++++++++++------------------------
target-ppc/mmu-hash64.c | 50 ++++++++++++++++++++++-------------------------
2 files changed, 45 insertions(+), 53 deletions(-)
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index 8b403fe..53e86de 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -295,31 +295,8 @@ static int ppc_hash32_direct_store(CPUPPCState *env,
target_ulong sr,
}
}
-static int pte_check_hash32(struct mmu_ctx_hash32 *ctx, target_ulong pte0,
- target_ulong pte1, int rwx)
-{
- int access, ret, pp;
-
- pp = pte1 & HPTE32_R_PP;
- /* Compute access rights */
- access = ppc_hash32_pp_check(ctx->key, pp, ctx->nx);
- /* Keep the matching PTE informations */
- ctx->raddr = pte1;
- ctx->prot = access;
- ret = ppc_hash32_check_prot(ctx->prot, rwx);
- if (ret == 0) {
- /* Access granted */
- LOG_MMU("PTE access granted !\n");
- } else {
- /* Access right violation */
- LOG_MMU("PTE access rejected\n");
- }
-
- return ret;
-}
-
-static int ppc_hash32_pte_update_flags(struct mmu_ctx_hash32 *ctx,
- uint32_t *pte1p, int ret, int rwx)
+static int ppc_hash32_pte_update_flags(struct mmu_ctx_hash32 *ctx, uint32_t
*pte1p,
+ int ret, int rwx)
{
int store = 0;
@@ -420,6 +397,8 @@ static int ppc_hash32_translate(CPUPPCState *env, struct
mmu_ctx_hash32 *ctx,
hwaddr pte_offset;
ppc_hash_pte32_t pte;
+ assert((rwx == 0) || (rwx == 1) || (rwx == 2));
+
/* 1. Handle real mode accesses */
if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
/* Translation is off */
@@ -461,7 +440,24 @@ static int ppc_hash32_translate(CPUPPCState *env, struct
mmu_ctx_hash32 *ctx,
/* 7. Check access permissions */
ctx->key = (((sr & SR32_KP) && (msr_pr != 0)) ||
((sr & SR32_KS) && (msr_pr == 0))) ? 1 : 0;
- ret = pte_check_hash32(ctx, pte.pte0, pte.pte1, rwx);
+
+ int access, pp;
+
+ pp = pte.pte1 & HPTE32_R_PP;
+ /* Compute access rights */
+ access = ppc_hash32_pp_check(ctx->key, pp, ctx->nx);
+ /* Keep the matching PTE informations */
+ ctx->raddr = pte.pte1;
+ ctx->prot = access;
+ ret = ppc_hash32_check_prot(ctx->prot, rwx);
+ if (ret == 0) {
+ /* Access granted */
+ LOG_MMU("PTE access granted !\n");
+ } else {
+ /* Access right violation */
+ LOG_MMU("PTE access rejected\n");
+ }
+
/* Update page flags */
if (ppc_hash32_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
ppc_hash32_store_hpte1(env, pte_offset, pte.pte1);
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 10372f0..2e109f4 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -297,32 +297,6 @@ static int ppc_hash64_check_prot(int prot, int rwx)
return ret;
}
-static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0,
- target_ulong pte1, int rwx)
-{
- int access, ret, pp;
- bool nx;
-
- pp = (pte1 & HPTE64_R_PP) | ((pte1 & HPTE64_R_PP0) >> 61);
- /* No execute if either noexec or guarded bits set */
- nx = (pte1 & HPTE64_R_N) || (pte1 & HPTE64_R_G);
- /* Compute access rights */
- access = ppc_hash64_pp_check(ctx->key, pp, nx);
- /* Keep the matching PTE informations */
- ctx->raddr = pte1;
- ctx->prot = access;
- ret = ppc_hash64_check_prot(ctx->prot, rwx);
- if (ret == 0) {
- /* Access granted */
- LOG_MMU("PTE access granted !\n");
- } else {
- /* Access right violation */
- LOG_MMU("PTE access rejected\n");
- }
-
- return ret;
-}
-
static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx,
uint64_t *pte1p, int ret, int rw)
{
@@ -439,6 +413,8 @@ static int ppc_hash64_translate(CPUPPCState *env, struct
mmu_ctx_hash64 *ctx,
ppc_hash_pte64_t pte;
int target_page_bits;
+ assert((rwx == 0) || (rwx == 1) || (rwx == 2));
+
/* 1. Handle real mode accesses */
if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
/* Translation is off */
@@ -471,7 +447,27 @@ static int ppc_hash64_translate(CPUPPCState *env, struct
mmu_ctx_hash64 *ctx,
ctx->key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
: (slb->vsid & SLB_VSID_KS));
- ret = pte64_check(ctx, pte.pte0, pte.pte1, rwx);
+
+ int access, pp;
+ bool nx;
+
+ pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
+ /* No execute if either noexec or guarded bits set */
+ nx = (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G);
+ /* Compute access rights */
+ access = ppc_hash64_pp_check(ctx->key, pp, nx);
+ /* Keep the matching PTE informations */
+ ctx->raddr = pte.pte1;
+ ctx->prot = access;
+ ret = ppc_hash64_check_prot(ctx->prot, rwx);
+ if (ret == 0) {
+ /* Access granted */
+ LOG_MMU("PTE access granted !\n");
+ } else {
+ /* Access right violation */
+ LOG_MMU("PTE access rejected\n");
+ }
+
/* Update page flags */
if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
ppc_hash64_store_hpte1(env, pte_offset, pte.pte1);
--
1.7.10.4
- [Qemu-ppc] [PATCH 36/48] mmu-hash*: Don't update PTE flags when permission is denied, (continued)
- [Qemu-ppc] [PATCH 36/48] mmu-hash*: Don't update PTE flags when permission is denied, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 47/48] target-ppc: Move ppc tlb_fill implementation into mmu_helper.c, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 44/48] mmu-hash*: Merge translate and fault handling functions, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 48/48] target-ppc: Use QOM method dispatch for MMU fault handling, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 15/48] target-ppc: mmu_ctx_t should not be a global type, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 17/48] mmu-hash*: Add hash pte load/store helpers, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 03/48] target-ppc: Remove address check for logging, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 39/48] mmu-hash64: Factor SLB N bit into permissions bits, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 08/48] target-ppc: Rework get_physical_address(), David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 30/48] mmu-hash*: Fold pte_check*() logic into caller,
David Gibson <=
- [Qemu-ppc] [PATCH 38/48] mmu-hash*: Clean up permission checking, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 14/48] target-ppc: Disentangle BAT code for 32-bit hash MMUs, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 35/48] mmu-hash32: Don't look up page tables on BAT permission error, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 24/48] mmu-hash*: Cleanup segment-level NX check, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 07/48] target-ppc: Disentangle get_segment(), David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 32/48] mmu-hash32: Split BAT size logic from permissions logic, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 11/48] target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug(), David Gibson, 2013/03/12
- Re: [Qemu-ppc] [0/48] target-ppc: MMU implementation cleanup for hash MMUs, Alexander Graf, 2013/03/21