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[Qemu-ppc] [PATCH 44/64] kvm: ppc: booke206: use MMU API
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PATCH 44/64] kvm: ppc: booke206: use MMU API |
Date: |
Thu, 6 Oct 2011 10:05:46 +0200 |
From: Scott Wood <address@hidden>
Share the TLB array with KVM. This allows us to set the initial TLB
both on initial boot and reset, is useful for debugging, and could
eventually be used to support migration.
Signed-off-by: Scott Wood <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
hw/ppce500_mpc8544ds.c | 2 +
target-ppc/cpu.h | 2 +
target-ppc/kvm.c | 85 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+), 0 deletions(-)
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index b86a008..61151d8 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -189,6 +189,8 @@ static void mmubooke_create_initial_mapping(CPUState *env,
tlb->mas2 = va & TARGET_PAGE_MASK;
tlb->mas7_3 = pa & TARGET_PAGE_MASK;
tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
+
+ env->tlb_dirty = true;
}
static void mpc8544ds_cpu_reset_sec(void *opaque)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b8d42e0..3e7f797 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -934,6 +934,8 @@ struct CPUPPCState {
ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
/* 403 dedicated access protection registers */
target_ulong pb[4];
+ bool tlb_dirty; /* Set to non-zero when modifying TLB */
+ bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
#endif
/* Other registers */
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index f65b6e1..35a6f10 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -112,6 +112,52 @@ static int kvm_arch_sync_sregs(CPUState *cenv)
return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs);
}
+/* Set up a shared TLB array with KVM */
+static int kvm_booke206_tlb_init(CPUState *env)
+{
+ struct kvm_book3e_206_tlb_params params = {};
+ struct kvm_config_tlb cfg = {};
+ struct kvm_enable_cap encap = {};
+ unsigned int entries = 0;
+ int ret, i;
+
+ if (!kvm_enabled() ||
+ !kvm_check_extension(env->kvm_state, KVM_CAP_SW_TLB)) {
+ return 0;
+ }
+
+ assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
+
+ for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
+ params.tlb_sizes[i] = booke206_tlb_size(env, i);
+ params.tlb_ways[i] = booke206_tlb_ways(env, i);
+ entries += params.tlb_sizes[i];
+ }
+
+ assert(entries == env->nb_tlb);
+ assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
+
+ env->tlb_dirty = true;
+
+ cfg.array = (uintptr_t)env->tlb.tlbm;
+ cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
+ cfg.params = (uintptr_t)¶ms;
+ cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
+
+ encap.cap = KVM_CAP_SW_TLB;
+ encap.args[0] = (uintptr_t)&cfg;
+
+ ret = kvm_vcpu_ioctl(env, KVM_ENABLE_CAP, &encap);
+ if (ret < 0) {
+ fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
+ __func__, strerror(-ret));
+ return ret;
+ }
+
+ env->kvm_sw_tlb = true;
+ return 0;
+}
+
int kvm_arch_init_vcpu(CPUState *cenv)
{
int ret;
@@ -123,6 +169,15 @@ int kvm_arch_init_vcpu(CPUState *cenv)
idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv);
+ /* Some targets support access to KVM's guest TLB. */
+ switch (cenv->mmu_model) {
+ case POWERPC_MMU_BOOKE206:
+ ret = kvm_booke206_tlb_init(cenv);
+ break;
+ default:
+ break;
+ }
+
return ret;
}
@@ -130,6 +185,31 @@ void kvm_arch_reset_vcpu(CPUState *env)
{
}
+static void kvm_sw_tlb_put(CPUState *env)
+{
+ struct kvm_dirty_tlb dirty_tlb;
+ unsigned char *bitmap;
+ int ret;
+
+ if (!env->kvm_sw_tlb) {
+ return;
+ }
+
+ bitmap = g_malloc((env->nb_tlb + 7) / 8);
+ memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
+
+ dirty_tlb.bitmap = (uintptr_t)bitmap;
+ dirty_tlb.num_dirty = env->nb_tlb;
+
+ ret = kvm_vcpu_ioctl(env, KVM_DIRTY_TLB, &dirty_tlb);
+ if (ret) {
+ fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
+ __func__, strerror(-ret));
+ }
+
+ g_free(bitmap);
+}
+
int kvm_arch_put_registers(CPUState *env, int level)
{
struct kvm_regs regs;
@@ -167,6 +247,11 @@ int kvm_arch_put_registers(CPUState *env, int level)
if (ret < 0)
return ret;
+ if (env->tlb_dirty) {
+ kvm_sw_tlb_put(env);
+ env->tlb_dirty = false;
+ }
+
return ret;
}
--
1.6.0.2
- [Qemu-ppc] [PATCH 09/64] PPC: MPIC: Remove read functionality for WO registers, (continued)
- [Qemu-ppc] [PATCH 09/64] PPC: MPIC: Remove read functionality for WO registers, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 10/64] PPC: MPIC: Fix CI bit definitions, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 01/64] spapr: proper qdevification, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 30/64] MPC8544DS: Generate CPU nodes on init, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 19/64] PPC: bamboo: Use kvm api for freq and clock frequencies, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 13/64] PPC: E500: Generate IRQ lines for many CPUs, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 03/64] spapr: make irq customizable via qdev, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 11/64] PPC: Bump MPIC up to 32 supported CPUs, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 36/64] pseries: Bugfixes for interrupt numbering in XICS code, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 37/64] pseries: Add a phandle to the xicp interrupt controller device tree node, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 44/64] kvm: ppc: booke206: use MMU API,
Alexander Graf <=
- [Qemu-ppc] [PATCH 33/64] KVM: update kernel headers, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 56/64] PPC: Fix heathrow PIC to use little endian MMIO, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 14/64] device tree: add nop_node, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 02/64] spapr: prepare for qdevification of irq, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 07/64] PPC: Fix IPI support in MPIC, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 34/64] PPC: Enable to use PAPR with PR style KVM, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 64/64] ppc64: Fix linker script, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 28/64] device tree: give dt more size, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 12/64] PPC: E500: create multiple envs, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 59/64] KVM: PPC: Use HIOR setting for -M pseries with PR KVM, Alexander Graf, 2011/10/06