[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PATCH 36/64] pseries: Bugfixes for interrupt numbering in XI
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PATCH 36/64] pseries: Bugfixes for interrupt numbering in XICS code |
Date: |
Thu, 6 Oct 2011 10:05:38 +0200 |
From: David Gibson <address@hidden>
The implementation of the XICS interrupt controller contains several
(difficult to trigger) bugs due to the fact that we were not 100%
consistent with which irq numbering we used. In most places, global
numbers were used as handled by the presentation layer, however a few
functions took "local" numberings, that is the source number within
the interrupt source controller which is offset from the global
number. In most cases the function and its caller agreed on this, but
in a few cases it didn't.
This patch cleans this up by always using global numbering.
Translation to the local number is now always and only done when we
look up the individual interrupt source state structure. This should
remove the existing bugs and with luck reduce the chances of
re-introducing such bugs.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
hw/xics.c | 17 ++++++++---------
1 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/xics.c b/hw/xics.c
index 80e064e..1c5eaa4 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -185,17 +185,17 @@ static int ics_valid_irq(struct ics_state *ics, uint32_t
nr)
&& (nr < (ics->offset + ics->nr_irqs));
}
-static void ics_set_irq_msi(void *opaque, int nr, int val)
+static void ics_set_irq_msi(void *opaque, int srcno, int val)
{
struct ics_state *ics = (struct ics_state *)opaque;
- struct ics_irq_state *irq = ics->irqs + nr;
+ struct ics_irq_state *irq = ics->irqs + srcno;
if (val) {
if (irq->priority == 0xff) {
irq->masked_pending = 1;
/* masked pending */ ;
} else {
- icp_irq(ics->icp, irq->server, nr + ics->offset, irq->priority);
+ icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
}
}
}
@@ -227,7 +227,7 @@ static void ics_resend_msi(struct ics_state *ics)
static void ics_write_xive_msi(struct ics_state *ics, int nr, int server,
uint8_t priority)
{
- struct ics_irq_state *irq = ics->irqs + nr;
+ struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
irq->server = server;
irq->priority = priority;
@@ -237,7 +237,7 @@ static void ics_write_xive_msi(struct ics_state *ics, int
nr, int server,
}
irq->masked_pending = 0;
- icp_irq(ics->icp, server, nr + ics->offset, priority);
+ icp_irq(ics->icp, server, nr, priority);
}
static void ics_reject(struct ics_state *ics, int nr)
@@ -332,7 +332,7 @@ static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t
token,
return;
}
- ics_write_xive_msi(ics, nr - ics->offset, server, priority);
+ ics_write_xive_msi(ics, nr, server, priority);
rtas_st(rets, 0, 0); /* Success */
}
@@ -386,7 +386,7 @@ static void rtas_int_off(sPAPREnvironment *spapr, uint32_t
token,
struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);
irq->saved_priority = irq->priority;
- ics_write_xive_msi(xics, nr - xics->offset, irq->server, 0xff);
+ ics_write_xive_msi(xics, nr, irq->server, 0xff);
#endif
rtas_st(rets, 0, 0); /* Success */
@@ -416,8 +416,7 @@ static void rtas_int_on(sPAPREnvironment *spapr, uint32_t
token,
#if 0
struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);
- ics_write_xive_msi(xics, nr - xics->offset,
- irq->server, irq->saved_priority);
+ ics_write_xive_msi(xics, nr, irq->server, irq->saved_priority);
#endif
rtas_st(rets, 0, 0); /* Success */
--
1.6.0.2
- [Qemu-ppc] [PATCH 05/64] PPC: Add CPU local MMIO regions to MPIC, (continued)
- [Qemu-ppc] [PATCH 05/64] PPC: Add CPU local MMIO regions to MPIC, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 29/64] MPC8544DS: Remove CPU nodes, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 09/64] PPC: MPIC: Remove read functionality for WO registers, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 10/64] PPC: MPIC: Fix CI bit definitions, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 01/64] spapr: proper qdevification, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 30/64] MPC8544DS: Generate CPU nodes on init, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 19/64] PPC: bamboo: Use kvm api for freq and clock frequencies, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 13/64] PPC: E500: Generate IRQ lines for many CPUs, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 03/64] spapr: make irq customizable via qdev, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 11/64] PPC: Bump MPIC up to 32 supported CPUs, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 36/64] pseries: Bugfixes for interrupt numbering in XICS code,
Alexander Graf <=
- [Qemu-ppc] [PATCH 37/64] pseries: Add a phandle to the xicp interrupt controller device tree node, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 44/64] kvm: ppc: booke206: use MMU API, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 33/64] KVM: update kernel headers, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 56/64] PPC: Fix heathrow PIC to use little endian MMIO, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 14/64] device tree: add nop_node, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 02/64] spapr: prepare for qdevification of irq, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 07/64] PPC: Fix IPI support in MPIC, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 34/64] PPC: Enable to use PAPR with PR style KVM, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 64/64] ppc64: Fix linker script, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 28/64] device tree: give dt more size, Alexander Graf, 2011/10/06