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[Qemu-ppc] [PATCH 07/64] PPC: Fix IPI support in MPIC
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PATCH 07/64] PPC: Fix IPI support in MPIC |
Date: |
Thu, 6 Oct 2011 10:05:09 +0200 |
The current IPI support in the MPIC code is incomplete and doesn't work. This
code adds proper support for IPIs in MPIC by using the IDE register to remember
which CPUs IPIs are still outstanding to. New triggers through the IPI trigger
register only add to the list of CPUs we want to IPI.
Signed-off-by: Alexander Graf <address@hidden>
---
v1 -> v2:
- Use MAX_IPI instead of hardcoded 4
Signed-off-by: Alexander Graf <address@hidden>
---
hw/openpic.c | 17 +++++++++++++++--
1 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index f7d5583..9710ac0 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -57,7 +57,7 @@
#define MAX_MBX 4
#define MAX_TMR 4
#define VECTOR_BITS 8
-#define MAX_IPI 0
+#define MAX_IPI 4
#define VID (0x00000000)
@@ -840,7 +840,9 @@ static void openpic_cpu_write_internal(void *opaque,
target_phys_addr_t addr,
case 0x60:
case 0x70:
idx = (addr - 0x40) >> 4;
- write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE, val);
+ /* we use IDE as mask which CPUs to deliver the IPI to still. */
+ write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE,
+ opp->src[opp->irq_ipi0 + idx].ide | val);
openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
break;
@@ -934,6 +936,17 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
target_phys_addr_t addr,
reset_bit(&src->ipvp, IPVP_ACTIVITY);
src->pending = 0;
}
+
+ if ((n_IRQ >= opp->irq_ipi0) && (n_IRQ < (opp->irq_ipi0 +
MAX_IPI))) {
+ src->ide &= ~(1 << idx);
+ if (src->ide && !test_bit(&src->ipvp, IPVP_SENSE)) {
+ /* trigger on CPUs that didn't know about it yet */
+ openpic_set_irq(opp, n_IRQ, 1);
+ openpic_set_irq(opp, n_IRQ, 0);
+ /* if all CPUs knew about it, set active bit again */
+ set_bit(&src->ipvp, IPVP_ACTIVITY);
+ }
+ }
}
break;
case 0xB0: /* PEOI */
--
1.6.0.2
- [Qemu-ppc] [PATCH 13/64] PPC: E500: Generate IRQ lines for many CPUs, (continued)
- [Qemu-ppc] [PATCH 13/64] PPC: E500: Generate IRQ lines for many CPUs, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 03/64] spapr: make irq customizable via qdev, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 11/64] PPC: Bump MPIC up to 32 supported CPUs, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 36/64] pseries: Bugfixes for interrupt numbering in XICS code, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 37/64] pseries: Add a phandle to the xicp interrupt controller device tree node, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 44/64] kvm: ppc: booke206: use MMU API, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 33/64] KVM: update kernel headers, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 56/64] PPC: Fix heathrow PIC to use little endian MMIO, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 14/64] device tree: add nop_node, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 02/64] spapr: prepare for qdevification of irq, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 07/64] PPC: Fix IPI support in MPIC,
Alexander Graf <=
- [Qemu-ppc] [PATCH 34/64] PPC: Enable to use PAPR with PR style KVM, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 64/64] ppc64: Fix linker script, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 28/64] device tree: give dt more size, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 12/64] PPC: E500: create multiple envs, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 59/64] KVM: PPC: Use HIOR setting for -M pseries with PR KVM, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 46/64] ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 45/64] ppc: booke206: add "info tlb" support, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 08/64] PPC: Set MPIC IDE for IPI to 0, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 63/64] pseries: Implement set-time-of-day RTAS function, Alexander Graf, 2011/10/06
- [Qemu-ppc] [PATCH 62/64] pseries: Refactor spapr irq allocation, Alexander Graf, 2011/10/06