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Re: can't acknowledge non-secure group 1 interrupt during EL3 execution
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From: |
Peter Maydell |
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Subject: |
Re: can't acknowledge non-secure group 1 interrupt during EL3 execution |
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Date: |
Mon, 10 May 2021 16:09:50 +0100 |
On Thu, 6 May 2021 at 09:09, Peter Maydell <peter.maydell@linaro.org> wrote:
> I think there is a QEMU bug here -- we assume that the combination of
> "which register" and "is the CPU secure" is enough to identify a single
> valid interrupt group, and don't account for "in EL3 it could be either
> G1NS or G1".
I've now written a patch which I think should fix this:
https://patchew.org/QEMU/20210510150016.24910-1-peter.maydell@linaro.org/
-- PMM