RE: can't acknowledge non-secure group 1 interrupt during EL3 execution

[ckim]

Hi Peter Maydell,
Wow, thank you as always.
Now with the patch, the testbench works ok.
I'm happy my question here lead to a qemu patch. 😊
Thank you very much and best regards,
Chan Kim

> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Tuesday, May 11, 2021 12:10 AM
> To: Chan Kim <ckim@etri.re.kr>
> Cc: qemu-discuss <qemu-discuss@nongnu.org>
> Subject: Re: can't acknowledge non-secure group 1 interrupt during EL3
> execution
> 
> On Thu, 6 May 2021 at 09:09, Peter Maydell <peter.maydell@linaro.org>
> wrote:
> > I think there is a QEMU bug here -- we assume that the combination of
> > "which register" and "is the CPU secure" is enough to identify a
> > single valid interrupt group, and don't account for "in EL3 it could
> > be either G1NS or G1".
> 
> I've now written a patch which I think should fix this:
> https://patchew.org/QEMU/20210510150016.24910-1-peter.maydell@linaro.org/
> 
> -- PMM