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[PATCH 6/8] hw/arm/vexpress: Explicit number of GIC external IRQs
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 6/8] hw/arm/vexpress: Explicit number of GIC external IRQs |
Date: |
Thu, 30 Jan 2025 19:24:39 +0100 |
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Versatile Express board however expects a fixed set of 64
interrupts (see the fixed IRQ length when this board was added in
commit 2055283bcc8 ("hw/vexpress: Add model of ARM Versatile Express
board"). Add the GIC_EXT_IRQS definition (with a comment) to make
that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/vexpress.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 42c67034061..8e801aa79cb 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -51,6 +51,14 @@
#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
+/*
+ * The Cortex-A9MP/A15MP may have anything from 0 to 224 external interrupt
+ * IRQ lines (with another 32 internal). We default to 64+32, which
+ * is the number provided by the Cortex-A9MP test chip in the
+ * Realview PBX-A9 and Versatile Express A9 development boards.
+ */
+#define GIC_EXT_IRQS 64
+
/* Number of virtio transports to create (0..8; limited by
* number of available IRQ lines).
*/
@@ -241,6 +249,7 @@ static void init_cpus(MachineState *ms, const char
*cpu_type,
*/
dev = qdev_new(privdev);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
+ qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, periphbase);
@@ -251,7 +260,7 @@ static void init_cpus(MachineState *ms, const char
*cpu_type,
* external interrupts starting from 32 (because there
* are internal interrupts 0..31).
*/
- for (n = 0; n < 64; n++) {
+ for (n = 0; n < GIC_EXT_IRQS; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
@@ -543,7 +552,7 @@ static void vexpress_common_init(MachineState *machine)
VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
VEDBoardInfo *daughterboard = vmc->daughterboard;
DeviceState *dev, *sysctl, *pl041;
- qemu_irq pic[64];
+ qemu_irq pic[GIC_EXT_IRQS];
uint32_t sys_id;
DriveInfo *dinfo;
PFlashCFI01 *pflash0;
--
2.47.1
- [PATCH 0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore, Philippe Mathieu-Daudé, 2025/01/30
- [PATCH 1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition, Philippe Mathieu-Daudé, 2025/01/30
- [PATCH 2/8] hw/arm/exynos4210: Explicit number of GIC external IRQs, Philippe Mathieu-Daudé, 2025/01/30
- [PATCH 3/8] hw/arm/realview: Explicit number of GIC external IRQs, Philippe Mathieu-Daudé, 2025/01/30
- [PATCH 4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL, Philippe Mathieu-Daudé, 2025/01/30
- [PATCH 5/8] hw/arm/xilinx_zynq: Explicit number of GIC external IRQs, Philippe Mathieu-Daudé, 2025/01/30
- [PATCH 6/8] hw/arm/vexpress: Explicit number of GIC external IRQs,
Philippe Mathieu-Daudé <=
- [PATCH 7/8] hw/arm/highbank: Explicit number of GIC external IRQs, Philippe Mathieu-Daudé, 2025/01/30
- [PATCH 8/8] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs, Philippe Mathieu-Daudé, 2025/01/30