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[PULL 42/68] tcg: Add TCGType argument to tcg_out_op
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From: |
Richard Henderson |
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Subject: |
[PULL 42/68] tcg: Add TCGType argument to tcg_out_op |
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Date: |
Fri, 17 Jan 2025 10:24:30 -0800 |
Pass TCGOp.type to the output function.
For aarch64 and tci, use this instead of testing TCG_OPF_64BIT.
For s390x, use this instead of testing INDEX_op_deposit_i64.
For i386, use this to initialize rexw.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 4 ++--
tcg/aarch64/tcg-target.c.inc | 6 +-----
tcg/arm/tcg-target.c.inc | 2 +-
tcg/i386/tcg-target.c.inc | 10 +++++-----
tcg/loongarch64/tcg-target.c.inc | 2 +-
tcg/mips/tcg-target.c.inc | 2 +-
tcg/ppc/tcg-target.c.inc | 2 +-
tcg/riscv/tcg-target.c.inc | 2 +-
tcg/s390x/tcg-target.c.inc | 7 +++----
tcg/sparc64/tcg-target.c.inc | 2 +-
tcg/tci/tcg-target.c.inc | 4 ++--
11 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 83356d932d..9b54a8bec8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -134,7 +134,7 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg,
tcg_target_long);
static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2);
static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg);
static void tcg_out_goto_tb(TCGContext *s, int which);
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS]);
#if TCG_TARGET_MAYBE_vec
@@ -5423,7 +5423,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
tcg_out_vec_op(s, op->opc, TCGOP_TYPE(op) - TCG_TYPE_V64,
TCGOP_VECE(op), new_args, const_args);
} else {
- tcg_out_op(s, op->opc, new_args, const_args);
+ tcg_out_op(s, op->opc, TCGOP_TYPE(op), new_args, const_args);
}
break;
}
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 9116f85667..ede6f47235 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2115,14 +2115,10 @@ void tb_target_set_jmp_target(const TranslationBlock
*tb, int n,
flush_idcache_range(jmp_rx, jmp_rw, 4);
}
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
- /* 99% of the time, we can signal the use of extension registers
- by looking to see if the opcode handles 64-bit data. */
- TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
-
/* Hoist the loads of the most common arguments. */
TCGArg a0 = args[0];
TCGArg a1 = args[1];
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 182cac1a8a..9cfb733a14 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1805,7 +1805,7 @@ void tb_target_set_jmp_target(const TranslationBlock *tb,
int n,
flush_idcache_range(jmp_rx, jmp_rw, 4);
}
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 64826c7419..8d1057cdb3 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2612,17 +2612,16 @@ void tb_target_set_jmp_target(const TranslationBlock
*tb, int n,
/* no need to flush icache explicitly */
}
-static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg args[TCG_MAX_OP_ARGS],
- const int const_args[TCG_MAX_OP_ARGS])
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0, a1, a2;
- int c, const_a2, vexop, rexw = 0;
+ int c, const_a2, vexop, rexw;
#if TCG_TARGET_REG_BITS == 64
# define OP_32_64(x) \
case glue(glue(INDEX_op_, x), _i64): \
- rexw = P_REXW; /* FALLTHRU */ \
case glue(glue(INDEX_op_, x), _i32)
#else
# define OP_32_64(x) \
@@ -2634,6 +2633,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
a1 = args[1];
a2 = args[2];
const_a2 = const_args[2];
+ rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
switch (opc) {
case INDEX_op_goto_ptr:
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 2f0d4d01ff..3dff29facb 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1278,7 +1278,7 @@ void tb_target_set_jmp_target(const TranslationBlock *tb,
int n,
flush_idcache_range(jmp_rx, jmp_rw, 4);
}
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index b89b279a0e..b31b8f0007 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1678,7 +1678,7 @@ void tb_target_set_jmp_target(const TranslationBlock *tb,
int n,
/* Always indirect, nothing to do */
}
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 1e7b8a204c..9205ac99e9 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2940,7 +2940,7 @@ void tb_target_set_jmp_target(const TranslationBlock *tb,
int n,
flush_idcache_range(jmp_rx, jmp_rw, 4);
}
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 432a2fe26f..e381ba4e77 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1960,7 +1960,7 @@ void tb_target_set_jmp_target(const TranslationBlock *tb,
int n,
flush_idcache_range(jmp_rx, jmp_rw, 4);
}
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index e09a726ecf..fc7d986e68 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2117,9 +2117,9 @@ void tb_target_set_jmp_target(const TranslationBlock *tb,
int n,
case glue(glue(INDEX_op_,x),_i32): \
case glue(glue(INDEX_op_,x),_i64)
-static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg args[TCG_MAX_OP_ARGS],
- const int const_args[TCG_MAX_OP_ARGS])
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
S390Opcode op, op2;
TCGArg a0, a1, a2;
@@ -2713,7 +2713,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
/* Since we can't support "0Z" as a constraint, we allow a1 in
any register. Fix things up as if a matching constraint. */
if (a0 != a1) {
- TCGType type = (opc == INDEX_op_deposit_i64);
if (a0 == a2) {
tcg_out_mov(s, type, TCG_TMP0, a2);
a2 = TCG_TMP0;
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index 48de490120..afc778fae7 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -1288,7 +1288,7 @@ void tb_target_set_jmp_target(const TranslationBlock *tb,
int n,
{
}
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 662acbdcb6..88cecbd62f 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -708,7 +708,7 @@ void tb_target_set_jmp_target(const TranslationBlock *tb,
int n,
/* Always indirect, nothing to do */
}
-static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
@@ -790,7 +790,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */
{
TCGArg pos = args[2], len = args[3];
- TCGArg max = tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 32;
+ TCGArg max = type == TCG_TYPE_I32 ? 32 : 64;
tcg_debug_assert(pos < max);
tcg_debug_assert(pos + len <= max);
--
2.43.0
- [PULL 37/68] tcg: Remove args_ct from TCGOpDef, (continued)
- [PULL 37/68] tcg: Remove args_ct from TCGOpDef, Richard Henderson, 2025/01/17
- [PULL 28/68] tcg/s390x: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h', Richard Henderson, 2025/01/17
- [PULL 29/68] tcg/sparc64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h', Richard Henderson, 2025/01/17
- [PULL 34/68] tcg: Use C_NotImplemented in tcg_target_op_def, Richard Henderson, 2025/01/17
- [PULL 33/68] tcg: Split out tcg-target-mo.h, Richard Henderson, 2025/01/17
- [PULL 38/68] tcg: Constify tcg_op_defs, Richard Henderson, 2025/01/17
- [PULL 36/68] tcg: Reorg process_op_defs, Richard Henderson, 2025/01/17
- [PULL 39/68] tcg: Validate op supported in opcode_args_ct, Richard Henderson, 2025/01/17
- [PULL 41/68] tcg: Pass type and flags to tcg_target_op_def, Richard Henderson, 2025/01/17
- [PULL 40/68] tcg: Add TCG_OPF_NOT_PRESENT to opcodes without inputs or outputs, Richard Henderson, 2025/01/17
- [PULL 42/68] tcg: Add TCGType argument to tcg_out_op,
Richard Henderson <=
- [PULL 43/68] tcg: Remove TCG_OPF_64BIT, Richard Henderson, 2025/01/17
- [PULL 45/68] tcg: Replace IMPLVEC with TCG_OPF_VECTOR, Richard Henderson, 2025/01/17
- [PULL 48/68] tcg/i386: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/17
- [PULL 44/68] tcg: Drop implementation checks from tcg-opc.h, Richard Henderson, 2025/01/17
- [PULL 46/68] tcg/mips: Expand bswap unconditionally, Richard Henderson, 2025/01/17
- [PULL 50/68] tcg/aarch64: Expand extract with offset 0 with andi, Richard Henderson, 2025/01/17
- [PULL 52/68] tcg/loongarch64: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/17
- [PULL 53/68] tcg/mips: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/17
- [PULL 57/68] tcg/s390x: Fold the ext{8, 16, 32}[us] cases into {s}extract, Richard Henderson, 2025/01/17
- [PULL 58/68] tcg/sparc64: Use SRA, SRL for {s}extract_i64, Richard Henderson, 2025/01/17