[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 17/48] intel_iommu: Add an internal API to find an address space w
From: |
Michael S. Tsirkin |
Subject: |
[PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID |
Date: |
Wed, 15 Jan 2025 13:09:20 -0500 |
From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
This will be used to implement the device IOTLB invalidation
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-13-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu.c | 40 ++++++++++++++++++++++++----------------
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index c45a486bf8..9aa807593e 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -70,6 +70,11 @@ struct vtd_hiod_key {
uint8_t devfn;
};
+struct vtd_as_raw_key {
+ uint16_t sid;
+ uint32_t pasid;
+};
+
struct vtd_iotlb_key {
uint64_t gfn;
uint32_t pasid;
@@ -1859,29 +1864,32 @@ static inline bool vtd_is_interrupt_addr(hwaddr addr)
return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
}
-static gboolean vtd_find_as_by_sid(gpointer key, gpointer value,
- gpointer user_data)
+static gboolean vtd_find_as_by_sid_and_pasid(gpointer key, gpointer value,
+ gpointer user_data)
{
struct vtd_as_key *as_key = (struct vtd_as_key *)key;
- uint16_t target_sid = *(uint16_t *)user_data;
+ struct vtd_as_raw_key *target = (struct vtd_as_raw_key *)user_data;
uint16_t sid = PCI_BUILD_BDF(pci_bus_num(as_key->bus), as_key->devfn);
- return sid == target_sid;
+
+ return (as_key->pasid == target->pasid) && (sid == target->sid);
+}
+
+static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(IntelIOMMUState *s,
+ uint16_t sid,
+ uint32_t pasid)
+{
+ struct vtd_as_raw_key key = {
+ .sid = sid,
+ .pasid = pasid
+ };
+
+ return g_hash_table_find(s->vtd_address_spaces,
+ vtd_find_as_by_sid_and_pasid, &key);
}
static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)
{
- uint8_t bus_num = PCI_BUS_NUM(sid);
- VTDAddressSpace *vtd_as = s->vtd_as_cache[bus_num];
-
- if (vtd_as &&
- (sid == PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn))) {
- return vtd_as;
- }
-
- vtd_as = g_hash_table_find(s->vtd_address_spaces, vtd_find_as_by_sid,
&sid);
- s->vtd_as_cache[bus_num] = vtd_as;
-
- return vtd_as;
+ return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID);
}
static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
--
MST
- [PULL 10/48] intel_iommu: Rename slpte to pte, (continued)
- [PULL 10/48] intel_iommu: Rename slpte to pte, Michael S. Tsirkin, 2025/01/15
- [PULL 12/48] intel_iommu: Check if the input address is canonical, Michael S. Tsirkin, 2025/01/15
- [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range, Michael S. Tsirkin, 2025/01/15
- [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes, Michael S. Tsirkin, 2025/01/15
- [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table, Michael S. Tsirkin, 2025/01/15
- [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument, Michael S. Tsirkin, 2025/01/15
- [PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation, Michael S. Tsirkin, 2025/01/15
- [PULL 27/48] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED, Michael S. Tsirkin, 2025/01/15
- [PULL 34/48] acpi/ghes: don't check if physical_address is not zero, Michael S. Tsirkin, 2025/01/15
- [PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID,
Michael S. Tsirkin <=
- [PULL 19/48] intel_iommu: piotlb invalidation should notify unmap, Michael S. Tsirkin, 2025/01/15
- [PULL 24/48] intel_iommu: Introduce a property to control FS1GP cap bit setting, Michael S. Tsirkin, 2025/01/15
- [PULL 14/48] intel_iommu: Set accessed and dirty bits during stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 18/48] intel_iommu: Add support for PASID-based device IOTLB invalidation, Michael S. Tsirkin, 2025/01/15
- [PULL 33/48] acpi/ghes: Change the type for source_id, Michael S. Tsirkin, 2025/01/15
- [PULL 32/48] acpi/ghes: Remove a duplicated out of bounds check, Michael S. Tsirkin, 2025/01/15
- [PULL 15/48] intel_iommu: Flush stage-1 cache in iotlb invalidation, Michael S. Tsirkin, 2025/01/15
- [PULL 16/48] intel_iommu: Process PASID-based iotlb invalidation, Michael S. Tsirkin, 2025/01/15
- [PULL 40/48] acpi/ghes: move offset calculus to a separate function, Michael S. Tsirkin, 2025/01/15
- [PULL 21/48] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2, Michael S. Tsirkin, 2025/01/15