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[PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation
From: |
Michael S. Tsirkin |
Subject: |
[PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation |
Date: |
Wed, 15 Jan 2025 13:09:50 -0500 |
From: Nicholas Piggin <npiggin@gmail.com>
The end vector calculation has a bug that results in polling fewer
than required vectors when reading at a non-zero offset in PBA memory.
Fixes: bbef882cc193 ("msi: add API to get notified about pending bit poll")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20241212120402.1475053-1-npiggin@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/pci/msix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index d8a55a6474..57ec7084a4 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -250,7 +250,7 @@ static uint64_t msix_pba_mmio_read(void *opaque, hwaddr
addr,
PCIDevice *dev = opaque;
if (dev->msix_vector_poll_notifier) {
unsigned vector_start = addr * 8;
- unsigned vector_end = MIN(addr + size * 8, dev->msix_entries_nr);
+ unsigned vector_end = MIN((addr + size) * 8, dev->msix_entries_nr);
dev->msix_vector_poll_notifier(dev, vector_start, vector_end);
}
--
MST
- [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation, (continued)
- [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation, Michael S. Tsirkin, 2025/01/15
- [PULL 11/48] intel_iommu: Implement stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 10/48] intel_iommu: Rename slpte to pte, Michael S. Tsirkin, 2025/01/15
- [PULL 12/48] intel_iommu: Check if the input address is canonical, Michael S. Tsirkin, 2025/01/15
- [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range, Michael S. Tsirkin, 2025/01/15
- [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes, Michael S. Tsirkin, 2025/01/15
- [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table, Michael S. Tsirkin, 2025/01/15
- [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument, Michael S. Tsirkin, 2025/01/15
- [PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation,
Michael S. Tsirkin <=
- [PULL 27/48] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED, Michael S. Tsirkin, 2025/01/15
- [PULL 34/48] acpi/ghes: don't check if physical_address is not zero, Michael S. Tsirkin, 2025/01/15
- [PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID, Michael S. Tsirkin, 2025/01/15
- [PULL 19/48] intel_iommu: piotlb invalidation should notify unmap, Michael S. Tsirkin, 2025/01/15
- [PULL 24/48] intel_iommu: Introduce a property to control FS1GP cap bit setting, Michael S. Tsirkin, 2025/01/15
- [PULL 14/48] intel_iommu: Set accessed and dirty bits during stage-1 translation, Michael S. Tsirkin, 2025/01/15
- [PULL 18/48] intel_iommu: Add support for PASID-based device IOTLB invalidation, Michael S. Tsirkin, 2025/01/15
- [PULL 33/48] acpi/ghes: Change the type for source_id, Michael S. Tsirkin, 2025/01/15
- [PULL 32/48] acpi/ghes: Remove a duplicated out of bounds check, Michael S. Tsirkin, 2025/01/15
- [PULL 15/48] intel_iommu: Flush stage-1 cache in iotlb invalidation, Michael S. Tsirkin, 2025/01/15