Re: [PATCH v3 0/3] Introduce a new Write Protected pin inverted property

[Cédric Le Goater]

On 1/7/25 23:36, Peter Maydell wrote:
> On Tue, 7 Jan 2025 at 17:55, Cédric Le Goater <clg@kaod.org> wrote:
> > Hello,
> >
> > > I would not recommend using qemu_irq_invert() in new code.
> > >
> > > I guess in an ideal world we'd implement a QOM object
> > > that encapsulated the the "not gate" logic, similar to
> > > TYPE_OR_IRQ. (Though for TYPE_OR_IRQ we made the mistake
> > > of making it inherit from TYPE_DEVICE, not TYPE_SYSBUS_DEVICE,
> > > so it doesn't get reset properly on system reset and so
> > > the "what happens to the output on reset" is still not
> > > really correct.)
> >
> > I see how this would work with TYPE_PL181 model but I don't
> > understand how this could work with TYPE_SYSBUS_SDHCI since
> > we don't have a gpio line to invert the level. Am I missing
> > something ?
>
> You have a gpio line, i.e. a qemu_irq, because you're passing
> it to qemu_irq_invert(), 

This part was proposed by Philippe and is not related to the
proposal.

I am not very familiar with these devices and AFAUI, the
SHDCIState irq being modified has a much broader scope than
a write protection toggle/level. I suppose the irq covers all
kind of transfers.

> and you could instead connect it into
> a hypothetical TYPE_NOT_IRQ device. qemu_irq are GPIO lines,
> the type just has an odd name for historical reasons.

Yes. I was looking for something like this but we don't have
a "card-read-only" GPIO line like in TYPE_PL181. Hence my
confusion.

Thanks,

C.