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[PATCH 46/73] tcg: Merge TCG_TARGET_HAS_extract2_{i32,i64}
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From: |
Richard Henderson |
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Subject: |
[PATCH 46/73] tcg: Merge TCG_TARGET_HAS_extract2_{i32,i64} |
|
Date: |
Thu, 2 Jan 2025 10:06:26 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-opc.h | 4 ++--
tcg/aarch64/tcg-target-has.h | 3 +--
tcg/arm/tcg-target-has.h | 2 +-
tcg/i386/tcg-target-has.h | 3 +--
tcg/loongarch64/tcg-target-has.h | 3 +--
tcg/mips/tcg-target-has.h | 2 --
tcg/ppc/tcg-target-has.h | 3 +--
tcg/riscv/tcg-target-has.h | 3 +--
tcg/s390x/tcg-target-has.h | 3 +--
tcg/sparc64/tcg-target-has.h | 3 +--
tcg/tcg-has.h | 1 -
tcg/tci/tcg-target-has.h | 3 +--
tcg/tcg-op.c | 38 ++++++++++++++++----------------
tcg/tcg.c | 4 ++--
14 files changed, 32 insertions(+), 43 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index d685b6915e..6082549322 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -79,7 +79,7 @@ DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I32)))
DEF(deposit_i32, 1, 2, 2, 0)
DEF(extract_i32, 1, 1, 2, 0)
DEF(sextract_i32, 1, 1, 2, 0)
-DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
+DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2(TCG_TYPE_I32)))
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
@@ -148,7 +148,7 @@ DEF(rotr_i64, 1, 2, 0, IMPL64 |
IMPL(TCG_TARGET_HAS_rot(TCG_TYPE_I64)))
DEF(deposit_i64, 1, 2, 2, IMPL64)
DEF(extract_i64, 1, 1, 2, IMPL64)
DEF(sextract_i64, 1, 1, 2, IMPL64)
-DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
+DEF(extract2_i64, 1, 2, 1, IMPL64 |
IMPL(TCG_TARGET_HAS_extract2(TCG_TYPE_I64)))
/* size changing ops */
DEF(ext_i32_i64, 1, 1, 0, IMPL64)
diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h
index e71a0ff060..2bcfed2761 100644
--- a/tcg/aarch64/tcg-target-has.h
+++ b/tcg/aarch64/tcg-target-has.h
@@ -27,6 +27,7 @@
#define TCG_TARGET_HAS_rem(T) 1
#define TCG_TARGET_HAS_rot(T) 1
#define TCG_TARGET_HAS_sub2(T) 1
+#define TCG_TARGET_HAS_extract2(T) 1
/* optional integer and vector instructions */
#define TCG_TARGET_HAS_andc(T) 1
@@ -40,7 +41,6 @@
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
@@ -50,7 +50,6 @@
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_extract2_i64 1
/*
* Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,
diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h
index 761ec1bf08..6489a20662 100644
--- a/tcg/arm/tcg-target-has.h
+++ b/tcg/arm/tcg-target-has.h
@@ -38,6 +38,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_rem(T) 0
#define TCG_TARGET_HAS_rot(T) 1
#define TCG_TARGET_HAS_sub2(T) 1
+#define TCG_TARGET_HAS_extract2(T) 1
/* optional integer and vector instructions */
#define TCG_TARGET_HAS_andc(T) 1
@@ -51,7 +52,6 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 0 /* and r0, r1, #0xff */
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h
index cad82fa162..e2a3513102 100644
--- a/tcg/i386/tcg-target-has.h
+++ b/tcg/i386/tcg-target-has.h
@@ -39,6 +39,7 @@
#define TCG_TARGET_HAS_negsetcond(T) 1
#define TCG_TARGET_HAS_rot(T) 1
#define TCG_TARGET_HAS_sub2(T) 1
+#define TCG_TARGET_HAS_extract2(T) 1
/* optional integer and vector instructions */
#define TCG_TARGET_HAS_andc(T) (T >= TCG_TYPE_V64 || have_bmi1)
@@ -52,7 +53,6 @@
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_extract2_i32 1
#if TCG_TARGET_REG_BITS == 64
/* Keep 32-bit values zero-extended in a register. */
@@ -63,7 +63,6 @@
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_extract2_i64 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
#else
#define TCG_TARGET_HAS_qemu_st8_i32 1
diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h
index 5f2084b6d1..c1a37cb524 100644
--- a/tcg/loongarch64/tcg-target-has.h
+++ b/tcg/loongarch64/tcg-target-has.h
@@ -24,6 +24,7 @@
#define TCG_TARGET_HAS_rem(T) 1
#define TCG_TARGET_HAS_rot(T) 1
#define TCG_TARGET_HAS_sub2(T) 0
+#define TCG_TARGET_HAS_extract2(T) 0
/* optional integer and vector instructions */
#define TCG_TARGET_HAS_andc(T) 1
@@ -33,7 +34,6 @@
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) 1
-#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
@@ -43,7 +43,6 @@
#define TCG_TARGET_HAS_qemu_st8_i32 0
/* 64-bit operations */
-#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
index 915c8719d2..658748110d 100644
--- a/tcg/mips/tcg-target-has.h
+++ b/tcg/mips/tcg-target-has.h
@@ -70,13 +70,11 @@ extern bool use_mips32r2_instructions;
#endif
/* optional instructions detected at runtime */
-#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
-#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
#endif
diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
index 5543386980..42fcccbb0c 100644
--- a/tcg/ppc/tcg-target-has.h
+++ b/tcg/ppc/tcg-target-has.h
@@ -31,6 +31,7 @@
#define TCG_TARGET_HAS_rem(T) 1
#define TCG_TARGET_HAS_rot(T) 1
#define TCG_TARGET_HAS_sub2(T) (T == TCG_TYPE_REG)
+#define TCG_TARGET_HAS_extract2(T) 0
/* optional integer and vector instructions */
#define TCG_TARGET_HAS_andc(T) 1
@@ -46,7 +47,6 @@
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
-#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
@@ -57,7 +57,6 @@
#define TCG_TARGET_HAS_ext8u_i64 0
#define TCG_TARGET_HAS_ext16u_i64 0
#define TCG_TARGET_HAS_ext32u_i64 0
-#define TCG_TARGET_HAS_extract2_i64 0
#endif
#define TCG_TARGET_HAS_qemu_ldst_i128 \
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
index 2ecf2bd971..d5530dc0d6 100644
--- a/tcg/riscv/tcg-target-has.h
+++ b/tcg/riscv/tcg-target-has.h
@@ -24,6 +24,7 @@
#define TCG_TARGET_HAS_rem(T) 1
#define TCG_TARGET_HAS_rot(T) (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_sub2(T) 1
+#define TCG_TARGET_HAS_extract2(T) 0
/* optional integer and vector instructions */
#define TCG_TARGET_HAS_andc(T) (T <= TCG_TYPE_REG && (cpuinfo &
CPUINFO_ZBB))
@@ -33,7 +34,6 @@
#define TCG_TARGET_HAS_not(T) 1
#define TCG_TARGET_HAS_orc(T) (T <= TCG_TYPE_REG && (cpuinfo &
CPUINFO_ZBB))
-#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
@@ -42,7 +42,6 @@
#define TCG_TARGET_HAS_setcond2 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
-#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h
index 6f6dc28fc7..c01a782f80 100644
--- a/tcg/s390x/tcg-target-has.h
+++ b/tcg/s390x/tcg-target-has.h
@@ -42,6 +42,7 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_negsetcond(T) 1
#define TCG_TARGET_HAS_rot(T) 1
#define TCG_TARGET_HAS_sub2(T) 1
+#define TCG_TARGET_HAS_extract2(T) 0
/* optional integer and vector instructions */
#define TCG_TARGET_HAS_andc(T) (T >= TCG_TYPE_V64 ||
HAVE_FACILITY(MISC_INSN_EXT3))
@@ -55,7 +56,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
@@ -65,7 +65,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_qemu_ldst_i128 1
diff --git a/tcg/sparc64/tcg-target-has.h b/tcg/sparc64/tcg-target-has.h
index 2edbd5802f..747ed1ab8f 100644
--- a/tcg/sparc64/tcg-target-has.h
+++ b/tcg/sparc64/tcg-target-has.h
@@ -28,6 +28,7 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_rem(T) 0
#define TCG_TARGET_HAS_rot(T) 0
#define TCG_TARGET_HAS_sub2(T) 1
+#define TCG_TARGET_HAS_extract2(T) 0
/* optional integer and vector instructions */
#define TCG_TARGET_HAS_andc(T) 1
@@ -41,7 +42,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_ext16s_i32 0
#define TCG_TARGET_HAS_ext8u_i32 0
#define TCG_TARGET_HAS_ext16u_i32 0
-#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
@@ -51,7 +51,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_ext8u_i64 0
#define TCG_TARGET_HAS_ext16u_i64 0
#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
diff --git a/tcg/tcg-has.h b/tcg/tcg-has.h
index 55852ef309..5649d36961 100644
--- a/tcg/tcg-has.h
+++ b/tcg/tcg-has.h
@@ -18,7 +18,6 @@
#define TCG_TARGET_HAS_ext8u_i64 0
#define TCG_TARGET_HAS_ext16u_i64 0
#define TCG_TARGET_HAS_ext32u_i64 0
-#define TCG_TARGET_HAS_extract2_i64 0
#endif
/* Only one of DIV or DIV2 should be defined. */
diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
index 5d85e0d96e..ffe2b0ef27 100644
--- a/tcg/tci/tcg-target-has.h
+++ b/tcg/tci/tcg-target-has.h
@@ -22,6 +22,7 @@
#define TCG_TARGET_HAS_rem(T) 1
#define TCG_TARGET_HAS_rot(T) 1
#define TCG_TARGET_HAS_sub2(T) 1
+#define TCG_TARGET_HAS_extract2(T) 0
/* optional integer and vector instructions */
#define TCG_TARGET_HAS_andc(T) 1
@@ -35,12 +36,10 @@
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_extr_i64_i32 0
-#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 6536afb9e5..9af6f326b6 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -911,7 +911,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
TCGv_i32 arg2,
t1 = tcg_temp_ebb_new_i32();
- if (TCG_TARGET_HAS_extract2_i32) {
+ if (TCG_TARGET_HAS_extract2(TCG_TYPE_I32)) {
if (ofs + len == 32) {
tcg_gen_shli_i32(t1, arg1, len);
tcg_gen_extract2_i32(ret, t1, arg2, len);
@@ -1130,7 +1130,7 @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al,
TCGv_i32 ah,
tcg_gen_mov_i32(ret, ah);
} else if (al == ah) {
tcg_gen_rotri_i32(ret, al, ofs);
- } else if (TCG_TARGET_HAS_extract2_i32) {
+ } else if (TCG_TARGET_HAS_extract2(TCG_TYPE_I32)) {
tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
} else {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
@@ -1873,7 +1873,7 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret,
TCGv_i64 arg1,
tcg_gen_movi_i32(TCGV_LOW(ret), 0);
}
} else if (right) {
- if (TCG_TARGET_HAS_extract2_i32) {
+ if (TCG_TARGET_HAS_extract2(TCG_TYPE_I32)) {
tcg_gen_extract2_i32(TCGV_LOW(ret),
TCGV_LOW(arg1), TCGV_HIGH(arg1), c);
} else {
@@ -1887,7 +1887,7 @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret,
TCGv_i64 arg1,
tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
}
} else {
- if (TCG_TARGET_HAS_extract2_i32) {
+ if (TCG_TARGET_HAS_extract2(TCG_TYPE_I32)) {
tcg_gen_extract2_i32(TCGV_HIGH(ret),
TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c);
} else {
@@ -2684,6 +2684,20 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
TCGv_i64 arg2,
tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
return;
}
+ if (TCG_TARGET_HAS_extract2(TCG_TYPE_I64)) {
+ if (ofs == 0 && TCG_TARGET_HAS_rot(TCG_TYPE_I64)) {
+ tcg_gen_extract2_i64(ret, arg1, arg2, len);
+ tcg_gen_rotli_i64(ret, ret, len);
+ return;
+ }
+ if (ofs + len == 64) {
+ t1 = tcg_temp_ebb_new_i64();
+ tcg_gen_shli_i64(t1, arg1, len);
+ tcg_gen_extract2_i64(ret, t1, arg2, len);
+ tcg_temp_free_i64(t1);
+ return;
+ }
+ }
} else {
if (ofs >= 32) {
tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
@@ -2701,19 +2715,6 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
TCGv_i64 arg2,
t1 = tcg_temp_ebb_new_i64();
- if (TCG_TARGET_HAS_extract2_i64) {
- if (ofs + len == 64) {
- tcg_gen_shli_i64(t1, arg1, len);
- tcg_gen_extract2_i64(ret, t1, arg2, len);
- goto done;
- }
- if (ofs == 0) {
- tcg_gen_extract2_i64(ret, arg1, arg2, len);
- tcg_gen_rotli_i64(ret, ret, len);
- goto done;
- }
- }
-
mask = (1ull << len) - 1;
if (ofs + len < 64) {
tcg_gen_andi_i64(t1, arg2, mask);
@@ -2723,7 +2724,6 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
TCGv_i64 arg2,
}
tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
tcg_gen_or_i64(ret, ret, t1);
- done:
tcg_temp_free_i64(t1);
}
@@ -3021,7 +3021,7 @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al,
TCGv_i64 ah,
tcg_gen_mov_i64(ret, ah);
} else if (al == ah) {
tcg_gen_rotri_i64(ret, al, ofs);
- } else if (TCG_TARGET_HAS_extract2_i64) {
+ } else if (TCG_TARGET_HAS_extract2(TCG_TYPE_I64)) {
tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
} else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3c1a253889..5b2ea74f12 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2226,7 +2226,7 @@ bool tcg_op_supported(TCGOpcode op, TCGType type)
case INDEX_op_rotr_i32:
return TCG_TARGET_HAS_rot(TCG_TYPE_I32);
case INDEX_op_extract2_i32:
- return TCG_TARGET_HAS_extract2_i32;
+ return TCG_TARGET_HAS_extract2(TCG_TYPE_I32);
case INDEX_op_add2_i32:
return TCG_TARGET_HAS_add2(TCG_TYPE_I32);
case INDEX_op_sub2_i32:
@@ -2320,7 +2320,7 @@ bool tcg_op_supported(TCGOpcode op, TCGType type)
case INDEX_op_rotr_i64:
return TCG_TARGET_REG_BITS == 64 && TCG_TARGET_HAS_rot(TCG_TYPE_I64);
case INDEX_op_extract2_i64:
- return TCG_TARGET_HAS_extract2_i64;
+ return TCG_TARGET_REG_BITS == 64 &&
TCG_TARGET_HAS_extract2(TCG_TYPE_I64);
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
return TCG_TARGET_HAS_extr_i64_i32;
--
2.43.0
- Re: [PATCH 72/73] tcg: Merge bswap operations, (continued)
- [PATCH 54/73] tcg: Pass TCGOp to tcg_target_op_def, Richard Henderson, 2025/01/02
- [PATCH 68/73] tcg: Merge integer shift operations, Richard Henderson, 2025/01/02
- [PATCH 70/73] tcg: Merge extract2 operations, Richard Henderson, 2025/01/02
- [PATCH 44/73] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}, Richard Henderson, 2025/01/02
- [PATCH 53/73] tcg: Use C_NotImplemented in tcg_target_op_def, Richard Henderson, 2025/01/02
- [PATCH 43/73] tcg/tci: Remove assertions for deposit and extract, Richard Henderson, 2025/01/02
- [PATCH 66/73] tcg: Merge brcond, setcond, negsetcond, movcond operations, Richard Henderson, 2025/01/02
- [PATCH 45/73] tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}, Richard Henderson, 2025/01/02
- [PATCH 46/73] tcg: Merge TCG_TARGET_HAS_extract2_{i32,i64},
Richard Henderson <=
- [PATCH 51/73] tcg: Constify tcg_op_defs, Richard Henderson, 2025/01/02
- [PATCH 56/73] tcg: Remove INDEX_op_qemu_st8_*_i32, Richard Henderson, 2025/01/02
- [PATCH 60/73] tcg: Change have_vec to has_type in tcg_op_supported, Richard Henderson, 2025/01/02
- [PATCH 64/73] tcg: Merge integer add2, sub2 operations, Richard Henderson, 2025/01/02
- [PATCH 62/73] tcg: Merge integer logical operations, Richard Henderson, 2025/01/02
- [PATCH 71/73] tcg: Merge host integer load/store operations, Richard Henderson, 2025/01/02
- [PATCH 49/73] tcg: Reorg process_op_defs, Richard Henderson, 2025/01/02
- [PATCH 73/73] tcg: Merge clz, ctz, ctpop operations, Richard Henderson, 2025/01/02