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[PATCH 53/73] tcg: Use C_NotImplemented in tcg_target_op_def
From: |
Richard Henderson |
Subject: |
[PATCH 53/73] tcg: Use C_NotImplemented in tcg_target_op_def |
Date: |
Thu, 2 Jan 2025 10:06:33 -0800 |
Return C_NotImplemented instead of asserting for opcodes
not implemented by the backend.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 12 ++++++------
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
tcg/i386/tcg-target.c.inc | 2 +-
tcg/loongarch64/tcg-target.c.inc | 2 +-
tcg/mips/tcg-target.c.inc | 2 +-
tcg/ppc/tcg-target.c.inc | 2 +-
tcg/riscv/tcg-target.c.inc | 2 +-
tcg/s390x/tcg-target.c.inc | 2 +-
tcg/sparc64/tcg-target.c.inc | 2 +-
tcg/tci/tcg-target.c.inc | 2 +-
11 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 7ba6c45824..095008ac25 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -871,6 +871,7 @@ static int tcg_out_pool_finalize(TCGContext *s)
#define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_n1_o1_i4_, O1, O2, I1, I2,
I3, I4),
typedef enum {
+ C_NotImplemented = -1,
#include "tcg-target-con-set.h"
} TCGConstraintSetIndex;
@@ -3326,7 +3327,7 @@ static void process_op_defs(TCGContext *s)
for (TCGOpcode op = 0; op < NB_OPS; op++) {
const TCGOpDef *def = &tcg_op_defs[op];
const TCGConstraintSet *tdefs;
- unsigned con_set;
+ TCGConstraintSetIndex con_set;
TCGType type;
if (def->flags & TCG_OPF_NOT_PRESENT) {
@@ -3342,11 +3343,10 @@ static void process_op_defs(TCGContext *s)
/*
* Macro magic should make it impossible, but double-check that
- * the array index is in range. Since the signness of an enum
- * is implementation defined, force the result to unsigned.
+ * the array index is in range.
*/
con_set = tcg_target_op_def(op);
- tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
+ tcg_debug_assert(con_set >= 0 && con_set <
ARRAY_SIZE(constraint_sets));
/* The constraint arguments must match TCGOpcode arguments. */
tdefs = &constraint_sets[con_set];
@@ -3359,7 +3359,7 @@ static const TCGArgConstraint *opcode_args_ct(const TCGOp
*op)
{
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
- unsigned con_set;
+ TCGConstraintSetIndex con_set;
if (def->flags & TCG_OPF_NOT_PRESENT) {
return empty_cts;
@@ -3368,7 +3368,7 @@ static const TCGArgConstraint *opcode_args_ct(const TCGOp
*op)
tcg_debug_assert(tcg_op_supported(opc, op->type));
con_set = tcg_target_op_def(opc);
- tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets));
+ tcg_debug_assert(con_set >= 0 && con_set < ARRAY_SIZE(constraint_sets));
return all_args_cts[con_set];
}
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index c0fe10e657..72e64c7dba 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -3149,7 +3149,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
return C_O1_I2(w, 0, w);
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index cd770d2e20..d0c39f7122 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2295,7 +2295,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_bitsel_vec:
return C_O1_I3(w, w, w, w);
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index c73f1039e1..b6b15723b4 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3908,7 +3908,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
return C_O1_I4(x, x, x, xO, x);
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 395579774d..900558d301 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -2401,7 +2401,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
return C_O1_I3(w, w, w, w);
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index a8987528e4..d2ace88aae 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2305,7 +2305,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
: C_O0_I4(rZ, rZ, r, r));
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 2b3d46af46..62110619f0 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -4374,7 +4374,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
return C_O1_I4(v, v, v, vZM, v);
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 9e981c5111..8e0a2d967e 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -2789,7 +2789,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_cmpsel_vec:
return C_O1_I4(v, v, vL, vK, vK);
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 9696ff6515..cb0b7ff25e 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -3449,7 +3449,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
: C_O1_I4(v, v, v, vZ, v));
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index caa462249f..c104636cf7 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc
@@ -1632,7 +1632,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
return C_O1_I2(r, r, r);
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 4ab19e93cc..57293e1458 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -178,7 +178,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r);
default:
- g_assert_not_reached();
+ return C_NotImplemented;
}
}
--
2.43.0
- [PATCH 50/73] tcg: Remove args_ct from TCGOpDef, (continued)
- [PATCH 50/73] tcg: Remove args_ct from TCGOpDef, Richard Henderson, 2025/01/02
- [PATCH 47/73] tcg: Make INDEX_op_extrh_i64_i32 mandatory, Richard Henderson, 2025/01/02
- [PATCH 48/73] tcg: Remove INDEX_op_ext{8,16,32}{us}, Richard Henderson, 2025/01/02
- [PATCH 59/73] tcg: Remove TCG_OPF_64BIT, Richard Henderson, 2025/01/02
- [PATCH 72/73] tcg: Merge bswap operations, Richard Henderson, 2025/01/02
- [PATCH 54/73] tcg: Pass TCGOp to tcg_target_op_def, Richard Henderson, 2025/01/02
- [PATCH 68/73] tcg: Merge integer shift operations, Richard Henderson, 2025/01/02
- [PATCH 70/73] tcg: Merge extract2 operations, Richard Henderson, 2025/01/02
- [PATCH 44/73] tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}, Richard Henderson, 2025/01/02
- [PATCH 53/73] tcg: Use C_NotImplemented in tcg_target_op_def,
Richard Henderson <=
- [PATCH 43/73] tcg/tci: Remove assertions for deposit and extract, Richard Henderson, 2025/01/02
- [PATCH 66/73] tcg: Merge brcond, setcond, negsetcond, movcond operations, Richard Henderson, 2025/01/02
- [PATCH 45/73] tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}, Richard Henderson, 2025/01/02
- [PATCH 46/73] tcg: Merge TCG_TARGET_HAS_extract2_{i32,i64}, Richard Henderson, 2025/01/02
- [PATCH 51/73] tcg: Constify tcg_op_defs, Richard Henderson, 2025/01/02
- [PATCH 56/73] tcg: Remove INDEX_op_qemu_st8_*_i32, Richard Henderson, 2025/01/02
- [PATCH 60/73] tcg: Change have_vec to has_type in tcg_op_supported, Richard Henderson, 2025/01/02
- [PATCH 64/73] tcg: Merge integer add2, sub2 operations, Richard Henderson, 2025/01/02