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[PULL 20/32] target/riscv: Support the version for ss1p13
From: |
Alistair Francis |
Subject: |
[PULL 20/32] target/riscv: Support the version for ss1p13 |
Date: |
Thu, 27 Jun 2024 20:00:41 +1000 |
From: "Fea.Wang" <fea.wang@sifive.com>
Add RISC-V privilege 1.13 support.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liwei1518@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240606135454.119186-7-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 +++++-
target/riscv/tcg/tcg-cpu.c | 4 ++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fd0f09c468..4760cb2cc1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1779,7 +1779,9 @@ static int priv_spec_from_str(const char *priv_spec_str)
{
int priv_version = -1;
- if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
+ if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) {
+ priv_version = PRIV_VERSION_1_13_0;
+ } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
priv_version = PRIV_VERSION_1_12_0;
} else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) {
priv_version = PRIV_VERSION_1_11_0;
@@ -1799,6 +1801,8 @@ const char *priv_spec_to_str(int priv_version)
return PRIV_VER_1_11_0_STR;
case PRIV_VERSION_1_12_0:
return PRIV_VER_1_12_0_STR;
+ case PRIV_VERSION_1_13_0:
+ return PRIV_VER_1_13_0_STR;
default:
return NULL;
}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 4c6141f947..eb6f7b9d12 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -318,6 +318,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
cpu->cfg.has_priv_1_12 = true;
}
+ if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
+ cpu->cfg.has_priv_1_13 = true;
+ }
+
/* zic64b is 1.12 or later */
cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
cpu->cfg.cbop_blocksize == 64 &&
--
2.45.2
- [PULL 10/32] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible', (continued)
- [PULL 10/32] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible', Alistair Francis, 2024/06/27
- [PULL 11/32] hw/riscv/virt.c: imsics DT: add '#msi-cells', Alistair Francis, 2024/06/27
- [PULL 13/32] target/riscv/kvm: handle the exit with debug reason, Alistair Francis, 2024/06/27
- [PULL 14/32] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG, Alistair Francis, 2024/06/27
- [PULL 12/32] target/riscv/kvm: add software breakpoints support, Alistair Francis, 2024/06/27
- [PULL 16/32] target/riscv: Define macros and variables for ss1p13, Alistair Francis, 2024/06/27
- [PULL 17/32] target/riscv: Add 'P1P13' bit in SMSTATEEN0, Alistair Francis, 2024/06/27
- [PULL 15/32] target/riscv: Reuse the conversion function of priv_spec, Alistair Francis, 2024/06/27
- [PULL 18/32] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Alistair Francis, 2024/06/27
- [PULL 19/32] target/riscv: Reserve exception codes for sw-check and hw-err, Alistair Francis, 2024/06/27
- [PULL 20/32] target/riscv: Support the version for ss1p13,
Alistair Francis <=
- [PULL 21/32] hw/riscv/virt.c: Make block devices default to virtio, Alistair Francis, 2024/06/27
- [PULL 22/32] target/riscv: Fix froundnx.h nanbox check, Alistair Francis, 2024/06/27
- [PULL 23/32] target/riscv: fix instructions count handling in icount mode, Alistair Francis, 2024/06/27
- [PULL 27/32] target/riscv: Add multi extension implied rules, Alistair Francis, 2024/06/27
- [PULL 25/32] target/riscv: Introduce extension implied rule helpers, Alistair Francis, 2024/06/27
- [PULL 26/32] target/riscv: Add MISA extension implied rules, Alistair Francis, 2024/06/27
- [PULL 24/32] target/riscv: Introduce extension implied rules definition, Alistair Francis, 2024/06/27
- [PULL 28/32] target/riscv: Add Zc extension implied rule, Alistair Francis, 2024/06/27
- [PULL 29/32] target/riscv: Remove extension auto-update check statements, Alistair Francis, 2024/06/27
- [PULL 31/32] target/riscv: Apply modularized matching conditions for watchpoint, Alistair Francis, 2024/06/27