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[PULL 12/32] target/riscv/kvm: add software breakpoints support
From: |
Alistair Francis |
Subject: |
[PULL 12/32] target/riscv/kvm: add software breakpoints support |
Date: |
Thu, 27 Jun 2024 20:00:33 +1000 |
From: Chao Du <duchao@eswincomputing.com>
This patch implements insert/remove software breakpoint process.
For RISC-V, GDB treats single-step similarly to breakpoint: add a
breakpoint at the next step address, then continue. So this also
works for single-step debugging.
Implement kvm_arch_update_guest_debug(): Set the control flag
when there are active breakpoints. This will help KVM to know
the status in the userspace.
Add some stubs which are necessary for building, and will be
implemented later.
Signed-off-by: Chao Du <duchao@eswincomputing.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240606014501.20763-2-duchao@eswincomputing.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm/kvm-cpu.c | 69 ++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 235e2cdaca..748fe5980f 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1969,3 +1969,72 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = {
};
DEFINE_TYPES(riscv_kvm_cpu_type_infos)
+
+static const uint32_t ebreak_insn = 0x00100073;
+static const uint16_t c_ebreak_insn = 0x9002;
+
+int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
+{
+ if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) {
+ return -EINVAL;
+ }
+
+ if ((bp->saved_insn & 0x3) == 0x3) {
+ if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0)
+ || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1))
{
+ return -EINVAL;
+ }
+ } else {
+ if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) {
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
+{
+ uint32_t ebreak;
+ uint16_t c_ebreak;
+
+ if ((bp->saved_insn & 0x3) == 0x3) {
+ if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) ||
+ ebreak != ebreak_insn ||
+ cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1))
{
+ return -EINVAL;
+ }
+ } else {
+ if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) ||
+ c_ebreak != c_ebreak_insn ||
+ cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1))
{
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
+{
+ /* TODO; To be implemented later. */
+ return -EINVAL;
+}
+
+int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
+{
+ /* TODO; To be implemented later. */
+ return -EINVAL;
+}
+
+void kvm_arch_remove_all_hw_breakpoints(void)
+{
+ /* TODO; To be implemented later. */
+}
+
+void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
+{
+ if (kvm_sw_breakpoints_active(cs)) {
+ dbg->control |= KVM_GUESTDBG_ENABLE;
+ }
+}
--
2.45.2
- [PULL 05/32] hw/riscv/virt.c: add aplic nodename helper, (continued)
- [PULL 05/32] hw/riscv/virt.c: add aplic nodename helper, Alistair Francis, 2024/06/27
- [PULL 04/32] hw/riscv/virt.c: add address-cells in create_fdt_one_aplic(), Alistair Francis, 2024/06/27
- [PULL 07/32] hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible', Alistair Francis, 2024/06/27
- [PULL 08/32] hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation', Alistair Francis, 2024/06/27
- [PULL 06/32] hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller', Alistair Francis, 2024/06/27
- [PULL 09/32] hw/riscv/virt.c: change imsic nodename to 'interrupt-controller', Alistair Francis, 2024/06/27
- [PULL 10/32] hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible', Alistair Francis, 2024/06/27
- [PULL 11/32] hw/riscv/virt.c: imsics DT: add '#msi-cells', Alistair Francis, 2024/06/27
- [PULL 13/32] target/riscv/kvm: handle the exit with debug reason, Alistair Francis, 2024/06/27
- [PULL 14/32] target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG, Alistair Francis, 2024/06/27
- [PULL 12/32] target/riscv/kvm: add software breakpoints support,
Alistair Francis <=
- [PULL 16/32] target/riscv: Define macros and variables for ss1p13, Alistair Francis, 2024/06/27
- [PULL 17/32] target/riscv: Add 'P1P13' bit in SMSTATEEN0, Alistair Francis, 2024/06/27
- [PULL 15/32] target/riscv: Reuse the conversion function of priv_spec, Alistair Francis, 2024/06/27
- [PULL 18/32] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Alistair Francis, 2024/06/27
- [PULL 19/32] target/riscv: Reserve exception codes for sw-check and hw-err, Alistair Francis, 2024/06/27
- [PULL 20/32] target/riscv: Support the version for ss1p13, Alistair Francis, 2024/06/27
- [PULL 21/32] hw/riscv/virt.c: Make block devices default to virtio, Alistair Francis, 2024/06/27
- [PULL 22/32] target/riscv: Fix froundnx.h nanbox check, Alistair Francis, 2024/06/27
- [PULL 23/32] target/riscv: fix instructions count handling in icount mode, Alistair Francis, 2024/06/27
- [PULL 27/32] target/riscv: Add multi extension implied rules, Alistair Francis, 2024/06/27