[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 28/32] target/riscv: Add Zc extension implied rule
|
From: |
Alistair Francis |
|
Subject: |
[PULL 28/32] target/riscv: Add Zc extension implied rule |
|
Date: |
Thu, 27 Jun 2024 20:00:49 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240625114629.27793-6-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 1a3aef5bff..ccca9037ed 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -925,11 +925,45 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu,
}
}
+/* Zc extension has special implied rules that need to be handled separately.
*/
+static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ CPURISCVState *env = &cpu->env;
+
+ if (cpu->cfg.ext_zce) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
+
+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+ }
+ }
+
+ /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */
+ if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+
+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+ }
+
+ if (riscv_has_ext(env, RVD)) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
+ }
+ }
+}
+
static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
{
RISCVCPUImpliedExtsRule *rule;
int i;
+ /* Enable the implied extensions for Zc. */
+ cpu_enable_zc_implied_rules(cpu);
+
/* Enable the implied MISAs. */
for (i = 0; (rule = riscv_misa_ext_implied_rules[i]); i++) {
if (riscv_has_ext(&cpu->env, rule->ext)) {
--
2.45.2
- [PULL 18/32] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, (continued)
- [PULL 18/32] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Alistair Francis, 2024/06/27
- [PULL 19/32] target/riscv: Reserve exception codes for sw-check and hw-err, Alistair Francis, 2024/06/27
- [PULL 20/32] target/riscv: Support the version for ss1p13, Alistair Francis, 2024/06/27
- [PULL 21/32] hw/riscv/virt.c: Make block devices default to virtio, Alistair Francis, 2024/06/27
- [PULL 22/32] target/riscv: Fix froundnx.h nanbox check, Alistair Francis, 2024/06/27
- [PULL 23/32] target/riscv: fix instructions count handling in icount mode, Alistair Francis, 2024/06/27
- [PULL 27/32] target/riscv: Add multi extension implied rules, Alistair Francis, 2024/06/27
- [PULL 25/32] target/riscv: Introduce extension implied rule helpers, Alistair Francis, 2024/06/27
- [PULL 26/32] target/riscv: Add MISA extension implied rules, Alistair Francis, 2024/06/27
- [PULL 24/32] target/riscv: Introduce extension implied rules definition, Alistair Francis, 2024/06/27
- [PULL 28/32] target/riscv: Add Zc extension implied rule,
Alistair Francis <=
- [PULL 29/32] target/riscv: Remove extension auto-update check statements, Alistair Francis, 2024/06/27
- [PULL 31/32] target/riscv: Apply modularized matching conditions for watchpoint, Alistair Francis, 2024/06/27
- [PULL 30/32] target/riscv: Add functions for common matching conditions of trigger, Alistair Francis, 2024/06/27
- [PULL 32/32] target/riscv: Apply modularized matching conditions for icount trigger, Alistair Francis, 2024/06/27
- Re: [PULL 00/32] riscv-to-apply queue, Richard Henderson, 2024/06/27