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[PULL 13/34] target/riscv: FIX xATP_MODE validation
From: |
Alistair Francis |
Subject: |
[PULL 13/34] target/riscv: FIX xATP_MODE validation |
Date: |
Fri, 8 Mar 2024 21:11:31 +1000 |
From: Irina Ryapolova <irina.ryapolova@syntacore.com>
The SATP register is an SXLEN-bit read/write WARL register. It means that CSR
fields are only defined
for a subset of bit encodings, but allow any value to be written while
guaranteeing to return a legal
value whenever read (See riscv-privileged-20211203, SATP CSR).
For example on rv64 we are trying to write to SATP CSR val = 0x1000000000000000
(SATP_MODE = 1 - Reserved for standard use)
and after that we are trying to read SATP_CSR. We read from the SATP CSR value
= 0x1000000000000000, which is not a correct
operation (return illegal value).
Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240109145923.37893-1-irina.ryapolova@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cc9cef3d85..805b972f6d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1295,8 +1295,8 @@ static RISCVException read_mstatus(CPURISCVState *env,
int csrno,
static bool validate_vm(CPURISCVState *env, target_ulong vm)
{
- return (vm & 0xf) <=
- satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
+ uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map;
+ return get_field(mode_supported, (1 << vm));
}
static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
--
2.44.0
- [PULL 06/34] linux-user/riscv: Sync hwprobe keys with Linux, (continued)
- [PULL 10/34] target/riscv: Reset henvcfg to zero, Alistair Francis, 2024/03/08
- [PULL 11/34] target/riscv: Gate hardware A/D PTE bit updating, Alistair Francis, 2024/03/08
- [PULL 12/34] target/riscv: Promote svade to a normal extension, Alistair Francis, 2024/03/08
- [PULL 13/34] target/riscv: FIX xATP_MODE validation,
Alistair Francis <=
- [PULL 14/34] target/riscv: UPDATE xATP write CSR, Alistair Francis, 2024/03/08
- [PULL 15/34] target/riscv: Add missing include guard in pmu.h, Alistair Francis, 2024/03/08
- [PULL 17/34] hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier, Alistair Francis, 2024/03/08
- [PULL 16/34] hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables, Alistair Francis, 2024/03/08
- [PULL 18/34] hw/riscv/virt.c: add virtio-iommu-pci hotplug support, Alistair Francis, 2024/03/08
- [PULL 19/34] hw/riscv/virt.c: make aclint compatible with 'qtest' accel, Alistair Francis, 2024/03/08
- [PULL 20/34] tests/libqos: add riscv/virt machine nodes, Alistair Francis, 2024/03/08