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| From: | lixianglai |
| Subject: | Re: [PATCH V2 1/1] target/loongarch: Fixed tlb huge page loading issue |
| Date: | Wed, 6 Mar 2024 11:52:18 +0800 |
| User-agent: | Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 |
On 3/4/24 20:21, lixianglai wrote:
Hi Richard:
On 3/4/24 17:51, Xianglai Li wrote:
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super large page (page size is 1G) to create the page table,
it is found that the content of the corresponding address space is abnormal,
resulting in the bios can not start the operating system and graphical interface normally.
The lddir and ldpte instruction emulation has
a problem with the use of super large page processing above level 2.
The page size is not correctly calculated,
resulting in the wrong page size of the table entry found by tlb.
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
Cc: maobibo@loongson.cn
Cc: Song Gao <gaosong@loongson.cn>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: zhaotianrui@loongson.cn
---
target/loongarch/cpu.h | 1 +
target/loongarch/tcg/tlb_helper.c | 21 ++++++++++++---------
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ec37579fd6..eab3e41c71 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -292,6 +292,7 @@ typedef struct CPUArchState {
uint32_t fcsr0_mask;
uint32_t cpucfg[21];
+ uint32_t lddir_ps;
This magical cpu state does not appear in the manual.
The hardware instruction manual is hosted on github at
https://github.com/loongson/LoongArch-Documentation
Are you sure that large pages above level 2 are really supported by LDDIR?
Yes,We have done tests on the physical cpu of loongarch64 and
it works fine with a level 2 large page on the physical cpu.
Some explanation from the hardware engineering side is required.
The description of lddir hardware manual is as follows:
Instruction formats:
|lddir rd, rj, level|
The|LDDIR|instruction is used for accessing directory entries during software page table walking.
If bit|[6]|of the general register|rj|is|0|, it means that the content of|rj|is the physical address of the
base address of the level page table at this time. In this case, the|LDDIR|instruction will access the level
page table according to the current TLB refill address, retrieve the base address of the corresponding
|level+1|page table, and write it to the general register|rd|.
reference:
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
4.2.5.1.|LDDIR|
Yes, I have this manual. Please highlight the portion of this description that corresponds to the LDDIR_PS variable that you add.
Sorry, I don't think I quite understand what you mean.
Do you mean that you want me to point out the detailed
description of LDDIR_PS in the manual
or suggest that I add a corresponding comment to the LDDIR_PS variable in the patch?
I think the description I quoted is missing a key part:
If bit [6] of
general register rj is 1, it means
that the content in rj is a large page (Huge
Page) page table entry. In this case, after executing the LDDRI instruction,
the value in the general register rj will
be written directly to the general register rd.
The LDDIR_PS
variable is not described in detail in the manual, but is only
an intermediate variable to assist in page size calculation
during tcg simulation.
However, in
section 5.4.2 TLB, we learned that TLB is divided into STLB and
MTLB.
The PS field
in MTLB has the same meaning as the variable LDDIR_PS we
defined.
Since TLB is
divided into parity entries, Therefore, when the TLB is
generated,
the size of
each parity entry becomes half, that is, LDDIR_PS-1.
It should be
noted here that all large-page tlb entries will be placed in the
MTLB, because the PS field is only meaningful in the MTLB.
Thanks,
Xianglai.
r~
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