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Re: [PATCH V2 1/1] target/loongarch: Fixed tlb huge page loading issue


From: Richard Henderson
Subject: Re: [PATCH V2 1/1] target/loongarch: Fixed tlb huge page loading issue
Date: Mon, 4 Mar 2024 18:34:42 -1000
User-agent: Mozilla Thunderbird

On 3/4/24 17:51, Xianglai Li wrote:
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super large page (page size is 1G) to create the page 
table,
it is found that the content of the corresponding address space is abnormal,
resulting in the bios can not start the operating system and graphical 
interface normally.

The lddir and ldpte instruction emulation has
a problem with the use of super large page processing above level 2.
The page size is not correctly calculated,
resulting in the wrong page size of the table entry found by tlb.

Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
Cc: maobibo@loongson.cn
Cc: Song Gao <gaosong@loongson.cn>
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Cc: zhaotianrui@loongson.cn
---
  target/loongarch/cpu.h            |  1 +
  target/loongarch/tcg/tlb_helper.c | 21 ++++++++++++---------
  2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ec37579fd6..eab3e41c71 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -292,6 +292,7 @@ typedef struct CPUArchState {
      uint32_t fcsr0_mask;
uint32_t cpucfg[21];
+    uint32_t lddir_ps;

This magical cpu state does not appear in the manual.
Are you sure that large pages above level 2 are really supported by LDDIR?

Some explanation from the hardware engineering side is required.


r~



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