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[PATCH v2 38/90] target/sparc: Move MOVcc, MOVR to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH v2 38/90] target/sparc: Move MOVcc, MOVR to decodetree |
Date: |
Mon, 16 Oct 2023 23:11:52 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 4 ++
target/sparc/translate.c | 103 +++++++++++++++++---------------------
2 files changed, 51 insertions(+), 56 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index fe0eacd779..a61d10be5a 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -205,3 +205,7 @@ SRL_i 10 ..... 100110 ..... 1 . 000000 ......
@shifti
SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti
Tcc 10 0 cond:4 111010 rs1:5 imm:1 cc:1 00000 rs2_or_imm:7
+
+MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11
+MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11
+MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index deea3015b1..0b0b9aa8d3 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4407,6 +4407,51 @@ TRANS(SLL_i, ALL, do_shift_i, a, true, true)
TRANS(SRL_i, ALL, do_shift_i, a, false, true)
TRANS(SRA_i, ALL, do_shift_i, a, false, false)
+static bool do_mov_cond(DisasContext *dc, DisasCompare *cmp, int rd, TCGv src2)
+{
+ TCGv dst = gen_load_gpr(dc, rd);
+
+ tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, cmp->c2, src2, dst);
+ gen_store_gpr(dc, rd, dst);
+ return advance_pc(dc);
+}
+
+static bool trans_MOVcc(DisasContext *dc, arg_MOVcc *a)
+{
+ TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
+ DisasCompare cmp;
+
+ if (src2 == NULL) {
+ return false;
+ }
+ gen_compare(&cmp, a->cc, a->cond, dc);
+ return do_mov_cond(dc, &cmp, a->rd, src2);
+}
+
+static bool trans_MOVfcc(DisasContext *dc, arg_MOVfcc *a)
+{
+ TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
+ DisasCompare cmp;
+
+ if (src2 == NULL) {
+ return false;
+ }
+ gen_fcompare(&cmp, a->cc, a->cond);
+ return do_mov_cond(dc, &cmp, a->rd, src2);
+}
+
+static bool trans_MOVR(DisasContext *dc, arg_MOVR *a)
+{
+ TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
+ DisasCompare cmp;
+
+ if (src2 == NULL) {
+ return false;
+ }
+ gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
+ return do_mov_cond(dc, &cmp, a->rd, src2);
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -4779,66 +4824,12 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
goto illegal_insn; /* WRTBR, WRHPR in decodetree */
#ifdef TARGET_SPARC64
case 0x2c: /* V9 movcc */
- {
- int cc = GET_FIELD_SP(insn, 11, 12);
- int cond = GET_FIELD_SP(insn, 14, 17);
- DisasCompare cmp;
- TCGv dst;
-
- if (insn & (1 << 18)) {
- if (cc == 0) {
- gen_compare(&cmp, 0, cond, dc);
- } else if (cc == 2) {
- gen_compare(&cmp, 1, cond, dc);
- } else {
- goto illegal_insn;
- }
- } else {
- gen_fcompare(&cmp, cc, cond);
- }
-
- /* The get_src2 above loaded the normal 13-bit
- immediate field, not the 11-bit field we have
- in movcc. But it did handle the reg case. */
- if (IS_IMM) {
- simm = GET_FIELD_SPs(insn, 0, 10);
- tcg_gen_movi_tl(cpu_src2, simm);
- }
-
- dst = gen_load_gpr(dc, rd);
- tcg_gen_movcond_tl(cmp.cond, dst,
- cmp.c1, cmp.c2,
- cpu_src2, dst);
- gen_store_gpr(dc, rd, dst);
- break;
- }
+ case 0x2f: /* V9 movr */
+ goto illegal_insn; /* in decodetree */
case 0x2e: /* V9 popc */
tcg_gen_ctpop_tl(cpu_dst, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
break;
- case 0x2f: /* V9 movr */
- {
- int cond = GET_FIELD_SP(insn, 10, 12);
- DisasCompare cmp;
- TCGv dst;
-
- gen_compare_reg(&cmp, cond, cpu_src1);
-
- /* The get_src2 above loaded the normal 13-bit
- immediate field, not the 10-bit field we have
- in movr. But it did handle the reg case. */
- if (IS_IMM) {
- simm = GET_FIELD_SPs(insn, 0, 9);
- tcg_gen_movi_tl(cpu_src2, simm);
- }
-
- dst = gen_load_gpr(dc, rd);
- tcg_gen_movcond_tl(cmp.cond, dst,
- cmp.c1, cmp.c2,
- cpu_src2, dst);
- gen_store_gpr(dc, rd, dst);
- break;
- }
#endif
default:
goto illegal_insn;
--
2.34.1
- [PATCH v2 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, (continued)
- [PATCH v2 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 27/90] target/sparc: Move WRWIM, WRPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 25/90] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 29/90] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 28/90] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 32/90] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 30/90] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 31/90] target/sparc: Move MULX to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 34/90] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 35/90] target/sparc: Move UDIV, SDIV to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 38/90] target/sparc: Move MOVcc, MOVR to decodetree,
Richard Henderson <=
- [PATCH v2 39/90] target/sparc: Move POPC to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 33/90] target/sparc: Move SUBC to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 36/90] target/sparc: Move TADD, TSUB, MULS to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 37/90] target/sparc: Move SLL, SRL, SRA to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 40/90] target/sparc: Convert remaining v8 coproc insns to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 42/90] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 41/90] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 46/90] target/sparc: Split out ldst functions with asi pre-computed, Richard Henderson, 2023/10/17
- [PATCH v2 44/90] target/sparc: Split out resolve_asi, Richard Henderson, 2023/10/17
- [PATCH v2 43/90] target/sparc: Move DONE, RETRY to decodetree, Richard Henderson, 2023/10/17