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[PATCH v2 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH v2 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree |
Date: |
Mon, 16 Oct 2023 23:11:40 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 10 +++++++
target/sparc/translate.c | 61 ++++++++++++++++++---------------------
2 files changed, 38 insertions(+), 33 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 6acf0f9403..850b5d58d0 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -85,6 +85,16 @@ RDHPR_htba 10 rd:5 101001 00101 0 0000000000000
RDHPR_hver 10 rd:5 101001 00110 0 0000000000000
RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000
+{
+ WRPSR 10 00000 110001 ..... . ............. @n_r_ri
+ SAVED 10 00000 110001 00000 0 0000000000000
+}
+RESTORED 10 00001 110001 00000 0 0000000000000
+# UA2005 ALLCLEAN
+# UA2005 OTHERW
+# UA2005 NORMALW
+# UA2005 INVALW
+
{
RDWIM 10 rd:5 101010 00000 0 0000000000000
RDPR_tpc 10 rd:5 101010 00000 0 0000000000000
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 59931c053f..a5058b5931 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -38,6 +38,7 @@
#ifdef TARGET_SPARC64
#define gen_helper_rdpsr(D, E) qemu_build_not_reached()
+#define gen_helper_wrpsr(E, S) qemu_build_not_reached()
#define gen_helper_power_down(E) g_assert_not_reached()
#else
#define gen_helper_rdccr(D, E) qemu_build_not_reached()
@@ -46,6 +47,8 @@
#define gen_helper_set_softint(E, S) qemu_build_not_reached()
#define gen_helper_clear_softint(E, S) qemu_build_not_reached()
#define gen_helper_write_softint(E, S) qemu_build_not_reached()
+#define gen_helper_saved ({ qemu_build_not_reached(); NULL; })
+#define gen_helper_restored ({ qemu_build_not_reached(); NULL; })
#endif
/* Dynamic PC, must exit to main loop. */
@@ -3806,6 +3809,31 @@ static void do_wrpowerdown(DisasContext *dc, TCGv src)
TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpowerdown)
+static void do_wrpsr(DisasContext *dc, TCGv src)
+{
+ gen_helper_wrpsr(tcg_env, src);
+ tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
+ dc->cc_op = CC_OP_FLAGS;
+ save_state(dc);
+ gen_op_next_insn();
+ tcg_gen_exit_tb(NULL, 0);
+ dc->base.is_jmp = DISAS_NORETURN;
+}
+
+TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr)
+
+static bool do_saved_restored(DisasContext *dc, void (*func)(TCGv_env))
+{
+ if (!supervisor(dc)) {
+ return raise_priv(dc);
+ }
+ func(tcg_env);
+ return advance_pc(dc);
+}
+
+TRANS(SAVED, 64, do_saved_restored, gen_helper_saved)
+TRANS(RESTORED, 64, do_saved_restored, gen_helper_restored)
+
static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a)
{
/*
@@ -4480,39 +4508,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
case 0x30:
goto illegal_insn; /* WRASR in decodetree */
#if !defined(CONFIG_USER_ONLY)
- case 0x31: /* wrpsr, V9 saved, restored */
- {
- if (!supervisor(dc))
- goto priv_insn;
-#ifdef TARGET_SPARC64
- switch (rd) {
- case 0:
- gen_helper_saved(tcg_env);
- break;
- case 1:
- gen_helper_restored(tcg_env);
- break;
- case 2: /* UA2005 allclean */
- case 3: /* UA2005 otherw */
- case 4: /* UA2005 normalw */
- case 5: /* UA2005 invalw */
- // XXX
- default:
- goto illegal_insn;
- }
-#else
- cpu_tmp0 = tcg_temp_new();
- tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
- gen_helper_wrpsr(tcg_env, cpu_tmp0);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
- dc->cc_op = CC_OP_FLAGS;
- save_state(dc);
- gen_op_next_insn();
- tcg_gen_exit_tb(NULL, 0);
- dc->base.is_jmp = DISAS_NORETURN;
-#endif
- }
- break;
case 0x32: /* wrwim, V9 wrpr */
{
if (!supervisor(dc))
--
2.34.1
- [PATCH v2 16/90] target/sparc: Merge gen_fcond with only caller, (continued)
- [PATCH v2 16/90] target/sparc: Merge gen_fcond with only caller, Richard Henderson, 2023/10/17
- [PATCH v2 18/90] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/17
- [PATCH v2 19/90] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 20/90] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 17/90] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/17
- [PATCH v2 21/90] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 22/90] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 08/90] target/sparc: Remove sparcv7 cpu features, Richard Henderson, 2023/10/17
- [PATCH v2 23/90] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 24/90] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree,
Richard Henderson <=
- [PATCH v2 27/90] target/sparc: Move WRWIM, WRPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 25/90] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 29/90] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 28/90] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 32/90] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 30/90] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 31/90] target/sparc: Move MULX to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 34/90] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 35/90] target/sparc: Move UDIV, SDIV to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 38/90] target/sparc: Move MOVcc, MOVR to decodetree, Richard Henderson, 2023/10/17