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[PATCH v2 31/90] target/sparc: Move MULX to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH v2 31/90] target/sparc: Move MULX to decodetree |
Date: |
Mon, 16 Oct 2023 23:11:45 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 6 +-----
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index abcee27fd4..d9474d2a20 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -171,5 +171,6 @@ XORN 10 ..... 000111 ..... . .............
@r_r_ri
XORNcc 10 ..... 010111 ..... . ............. @r_r_ri
ADDC 10 ..... 001000 ..... . ............. @r_r_ri
ADDCcc 10 ..... 011000 ..... . ............. @r_r_ri
+MULX 10 ..... 001001 ..... . ............. @r_r_ri
Tcc 10 0 cond:4 111010 rs1:5 imm:1 cc:1 00000 rs2_or_imm:7
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 27375c74ec..b3ce3947f3 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4183,6 +4183,7 @@ TRANS(SUB, ALL, do_arith, a, tcg_gen_sub_tl,
tcg_gen_subi_tl)
TRANS(ANDN, ALL, do_arith, a, tcg_gen_andc_tl, NULL)
TRANS(ORN, ALL, do_arith, a, tcg_gen_orc_tl, NULL)
TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL)
+TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl)
TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL)
TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl)
@@ -4654,11 +4655,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
-#ifdef TARGET_SPARC64
- case 0x9: /* V9 mulx */
- tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
- break;
-#endif
case 0xa: /* umul */
CHECK_IU_FEATURE(dc, MUL);
gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
--
2.34.1
- [PATCH v2 08/90] target/sparc: Remove sparcv7 cpu features, (continued)
- [PATCH v2 08/90] target/sparc: Remove sparcv7 cpu features, Richard Henderson, 2023/10/17
- [PATCH v2 23/90] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 24/90] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 27/90] target/sparc: Move WRWIM, WRPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 25/90] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 29/90] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 28/90] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 32/90] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 30/90] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 31/90] target/sparc: Move MULX to decodetree,
Richard Henderson <=
- [PATCH v2 34/90] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 35/90] target/sparc: Move UDIV, SDIV to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 38/90] target/sparc: Move MOVcc, MOVR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 39/90] target/sparc: Move POPC to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 33/90] target/sparc: Move SUBC to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 36/90] target/sparc: Move TADD, TSUB, MULS to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 37/90] target/sparc: Move SLL, SRL, SRA to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 40/90] target/sparc: Convert remaining v8 coproc insns to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 42/90] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 41/90] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/17