[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 06/22] target/arm: Drop unsupported_encoding() macro
From: |
Peter Maydell |
Subject: |
[PULL 06/22] target/arm: Drop unsupported_encoding() macro |
Date: |
Thu, 19 May 2022 18:36:35 +0100 |
The unsupported_encoding() macro logs a LOG_UNIMP message and then
generates code to raise the usual exception for an unallocated
encoding. Back when we were still implementing the A64 decoder this
was helpful for flagging up when guest code was using something we
hadn't yet implemented. Now we completely cover the A64 instruction
set it is barely used. The only remaining uses are for five
instructions whose semantics are "UNDEF, unless being run under
external halting debug":
* HLT (when not being used for semihosting)
* DCPSR1, DCPS2, DCPS3
* DRPS
QEMU doesn't implement external halting debug, so for us the UNDEF is
the architecturally correct behaviour (because it's not possible to
execute these instructions with halting debug enabled). The
LOG_UNIMP doesn't serve a useful purpose; replace these uses of
unsupported_encoding() with unallocated_encoding(), and delete the
macro.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220509160443.3561604-1-peter.maydell@linaro.org
---
target/arm/translate-a64.h | 9 ---------
target/arm/translate-a64.c | 8 ++++----
2 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 38884158aab..f2e8ee0ee1f 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -18,15 +18,6 @@
#ifndef TARGET_ARM_TRANSLATE_A64_H
#define TARGET_ARM_TRANSLATE_A64_H
-#define unsupported_encoding(s, insn) \
- do { \
- qemu_log_mask(LOG_UNIMP, \
- "%s:%d: unsupported instruction encoding 0x%08x " \
- "at pc=%016" PRIx64 "\n", \
- __FILE__, __LINE__, insn, s->pc_curr); \
- unallocated_encoding(s); \
- } while (0)
-
TCGv_i64 new_tmp_a64(DisasContext *s);
TCGv_i64 new_tmp_a64_local(DisasContext *s);
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 176a3c83ba2..f5025453078 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2127,13 +2127,13 @@ static void disas_exc(DisasContext *s, uint32_t insn)
* with our 32-bit semihosting).
*/
if (s->current_el == 0) {
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
break;
}
#endif
gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
} else {
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
}
break;
case 5:
@@ -2142,7 +2142,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
break;
}
/* DCPS1, DCPS2, DCPS3 */
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
break;
default:
unallocated_encoding(s);
@@ -2307,7 +2307,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
if (op3 != 0 || op4 != 0 || rn != 0x1f) {
goto do_unallocated;
} else {
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
}
return;
--
2.25.1
- [PULL 00/22] target-arm queue, Peter Maydell, 2022/05/19
- [PULL 03/22] target/arm: Implement FEAT_S2FWB, Peter Maydell, 2022/05/19
- [PULL 01/22] target/arm: Postpone interpretation of stage 2 descriptor attribute bits, Peter Maydell, 2022/05/19
- [PULL 05/22] target/arm: Implement FEAT_IDST, Peter Maydell, 2022/05/19
- [PULL 04/22] target/arm: Enable FEAT_S2FWB for -cpu max, Peter Maydell, 2022/05/19
- [PULL 07/22] hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters, Peter Maydell, 2022/05/19
- [PULL 09/22] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant, Peter Maydell, 2022/05/19
- [PULL 10/22] hw/intc/arm_gicv3: Support configurable number of physical priority bits, Peter Maydell, 2022/05/19
- [PULL 06/22] target/arm: Drop unsupported_encoding() macro,
Peter Maydell <=
- [PULL 02/22] target/arm: Factor out FWB=0 specific part of combine_cacheattrs(), Peter Maydell, 2022/05/19
- [PULL 12/22] hw/intc/arm_gicv3: Provide ich_num_aprs(), Peter Maydell, 2022/05/19
- [PULL 11/22] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU, Peter Maydell, 2022/05/19
- [PULL 14/22] hw/adc/zynq-xadc: Use qemu_irq typedef, Peter Maydell, 2022/05/19
- [PULL 15/22] target/arm/helper.c: Delete stray obsolete comment, Peter Maydell, 2022/05/19
- [PULL 13/22] Fix aarch64 debug register names., Peter Maydell, 2022/05/19
- [PULL 18/22] hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node, Peter Maydell, 2022/05/19
- [PULL 19/22] ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY, Peter Maydell, 2022/05/19
- [PULL 20/22] target/arm: Fix PAuth keys access checks for disabled SEL2, Peter Maydell, 2022/05/19
- [PULL 17/22] hw/arm/virt: Fix incorrect non-secure flash dtb node name, Peter Maydell, 2022/05/19