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[PULL 04/22] target/arm: Enable FEAT_S2FWB for -cpu max
From: |
Peter Maydell |
Subject: |
[PULL 04/22] target/arm: Enable FEAT_S2FWB for -cpu max |
Date: |
Thu, 19 May 2022 18:36:33 +0100 |
Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that
CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the
inherited CLIDR_EL1 value from the Cortex-A57 has them as 1).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220505183950.2781801-5-peter.maydell@linaro.org
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 8ed466bf68e..8f25502ced7 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -52,6 +52,7 @@ the following architecture extensions:
- FEAT_RAS (Reliability, availability, and serviceability)
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
- FEAT_RNG (Random number generator)
+- FEAT_S2FWB (Stage 2 forced Write-Back)
- FEAT_SB (Speculation Barrier)
- FEAT_SEL2 (Secure EL2)
- FEAT_SHA1 (SHA1 instructions)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 04427e073f1..e83c013e1fe 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -812,6 +812,7 @@ static void aarch64_max_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
uint64_t t;
+ uint32_t u;
if (kvm_enabled() || hvf_enabled()) {
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
@@ -842,6 +843,15 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
cpu->midr = t;
+ /*
+ * We're going to set FEAT_S2FWB, which mandates that
CLIDR_EL1.{LoUU,LoUIS}
+ * are zero.
+ */
+ u = cpu->clidr;
+ u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
+ u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
+ cpu->clidr = u;
+
t = cpu->isar.id_aa64isar0;
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
@@ -918,6 +928,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
+ t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
cpu->isar.id_aa64mmfr2 = t;
--
2.25.1
- [PULL 00/22] target-arm queue, Peter Maydell, 2022/05/19
- [PULL 03/22] target/arm: Implement FEAT_S2FWB, Peter Maydell, 2022/05/19
- [PULL 01/22] target/arm: Postpone interpretation of stage 2 descriptor attribute bits, Peter Maydell, 2022/05/19
- [PULL 05/22] target/arm: Implement FEAT_IDST, Peter Maydell, 2022/05/19
- [PULL 04/22] target/arm: Enable FEAT_S2FWB for -cpu max,
Peter Maydell <=
- [PULL 07/22] hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters, Peter Maydell, 2022/05/19
- [PULL 09/22] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant, Peter Maydell, 2022/05/19
- [PULL 10/22] hw/intc/arm_gicv3: Support configurable number of physical priority bits, Peter Maydell, 2022/05/19
- [PULL 06/22] target/arm: Drop unsupported_encoding() macro, Peter Maydell, 2022/05/19
- [PULL 02/22] target/arm: Factor out FWB=0 specific part of combine_cacheattrs(), Peter Maydell, 2022/05/19
- [PULL 12/22] hw/intc/arm_gicv3: Provide ich_num_aprs(), Peter Maydell, 2022/05/19
- [PULL 11/22] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU, Peter Maydell, 2022/05/19
- [PULL 14/22] hw/adc/zynq-xadc: Use qemu_irq typedef, Peter Maydell, 2022/05/19
- [PULL 15/22] target/arm/helper.c: Delete stray obsolete comment, Peter Maydell, 2022/05/19
- [PULL 13/22] Fix aarch64 debug register names., Peter Maydell, 2022/05/19