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[PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max
From: |
Alistair Francis |
Subject: |
[PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation |
Date: |
Mon, 20 Dec 2021 14:56:11 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-27-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 27 ++++++++++++++++---------
target/riscv/cpu_helper.c | 16 ++++++++++++---
target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++-
3 files changed, 42 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 709b7c3abb..11a0f41b27 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -430,18 +430,27 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
#endif
/*
- * A simplification for VLMAX
- * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
- * = (VLEN << LMUL) / (8 << SEW)
- * = (VLEN << LMUL) >> (SEW + 3)
- * = VLEN >> (SEW + 3 - LMUL)
+ * Encode LMUL to lmul as follows:
+ * LMUL vlmul lmul
+ * 1 000 0
+ * 2 001 1
+ * 4 010 2
+ * 8 011 3
+ * - 100 -
+ * 1/8 101 -3
+ * 1/4 110 -2
+ * 1/2 111 -1
+ *
+ * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
+ * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
+ * => VLMAX = vlen >> (1 + 3 - (-3))
+ * = 256 >> 7
+ * = 2
*/
static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
{
- uint8_t sew, lmul;
-
- sew = FIELD_EX64(vtype, VTYPE, VSEW);
- lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
+ uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
+ int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
return cpu->cfg.vlen >> (sew + 3 - lmul);
}
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1b31d0ad47..10f3baba53 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -75,12 +75,22 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
*pc,
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
+ /*
+ * If env->vl equals to VLMAX, we can use generic vector operation
+ * expanders (GVEC) to accerlate the vector operations.
+ * However, as LMUL could be a fractional number. The maximum
+ * vector size can be operated might be less than 8 bytes,
+ * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
+ * only when maxsz >= 8 bytes.
+ */
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
- bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+ uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
+ uint32_t maxsz = vlmax << sew;
+ bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
+ (maxsz >= 8);
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
FIELD_EX64(env->vtype, VTYPE, VILL));
- flags = FIELD_DP32(flags, TB_FLAGS, SEW,
- FIELD_EX64(env->vtype, VTYPE, VSEW));
+ flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
FIELD_EX64(env->vtype, VTYPE, VLMUL));
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index e12db9aae8..5c04ac90da 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1049,7 +1049,17 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
/*
*** Vector Integer Arithmetic Instructions
*/
-#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
+
+/*
+ * MAXSZ returns the maximum vector size can be operated in bytes,
+ * which is used in GVEC IR when vl_eq_vlmax flag is set to true
+ * to accerlate vector operation.
+ */
+static inline uint32_t MAXSZ(DisasContext *s)
+{
+ int scale = s->lmul - 3;
+ return scale < 0 ? s->vlen >> -scale : s->vlen << scale;
+}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
{
--
2.31.1
- [PULL 24/88] target/riscv: introduce more imm value modes in translator functions, (continued)
- [PULL 24/88] target/riscv: introduce more imm value modes in translator functions, Alistair Francis, 2021/12/19
- [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function, Alistair Francis, 2021/12/19
- [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions, Alistair Francis, 2021/12/19
- [PULL 27/88] target/riscv: rvv-1.0: configure instructions, Alistair Francis, 2021/12/19
- [PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions, Alistair Francis, 2021/12/19
- [PULL 29/88] target/riscv: rvv-1.0: index load and store instructions, Alistair Francis, 2021/12/19
- [PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns, Alistair Francis, 2021/12/19
- [PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load, Alistair Francis, 2021/12/19
- [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions, Alistair Francis, 2021/12/19
- [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Alistair Francis, 2021/12/19
- [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation,
Alistair Francis <=
- [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction, Alistair Francis, 2021/12/19
- [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction, Alistair Francis, 2021/12/19
- [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction, Alistair Francis, 2021/12/20
- [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions, Alistair Francis, 2021/12/20
- [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions, Alistair Francis, 2021/12/20
- [PULL 40/88] target/riscv: rvv-1.0: iota instruction, Alistair Francis, 2021/12/20
- [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended, Alistair Francis, 2021/12/20
- [PULL 41/88] target/riscv: rvv-1.0: element index instruction, Alistair Francis, 2021/12/20
- [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction, Alistair Francis, 2021/12/20
- [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions, Alistair Francis, 2021/12/20