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[PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of in
From: |
Alistair Francis |
Subject: |
[PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns |
Date: |
Mon, 20 Dec 2021 14:56:07 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-23-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index df45c1620c..3da4f3b1e6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -374,10 +374,10 @@ static target_ulong NAME(target_ulong base, \
return (base + *((ETYPE *)vs2 + H(idx))); \
}
-GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
-GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
-GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
-GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
+GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
+GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
+GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
+GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
static inline void
vext_ldst_index(void *vd, void *v0, target_ulong base,
--
2.31.1
- [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL, (continued)
- [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL, Alistair Francis, 2021/12/19
- [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations, Alistair Francis, 2021/12/19
- [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA, Alistair Francis, 2021/12/19
- [PULL 23/88] target/riscv: rvv-1.0: update check functions, Alistair Francis, 2021/12/19
- [PULL 24/88] target/riscv: introduce more imm value modes in translator functions, Alistair Francis, 2021/12/19
- [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function, Alistair Francis, 2021/12/19
- [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions, Alistair Francis, 2021/12/19
- [PULL 27/88] target/riscv: rvv-1.0: configure instructions, Alistair Francis, 2021/12/19
- [PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions, Alistair Francis, 2021/12/19
- [PULL 29/88] target/riscv: rvv-1.0: index load and store instructions, Alistair Francis, 2021/12/19
- [PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns,
Alistair Francis <=
- [PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load, Alistair Francis, 2021/12/19
- [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions, Alistair Francis, 2021/12/19
- [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Alistair Francis, 2021/12/19
- [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, Alistair Francis, 2021/12/19
- [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction, Alistair Francis, 2021/12/19
- [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction, Alistair Francis, 2021/12/19
- [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction, Alistair Francis, 2021/12/20
- [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions, Alistair Francis, 2021/12/20
- [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions, Alistair Francis, 2021/12/20
- [PULL 40/88] target/riscv: rvv-1.0: iota instruction, Alistair Francis, 2021/12/20