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[PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction
From: |
Alistair Francis |
Subject: |
[PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction |
Date: |
Mon, 20 Dec 2021 14:56:22 +1000 |
From: Frank Chang <frank.chang@sifive.com>
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-38-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index c250943dde..2c8002af54 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2461,9 +2461,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->lmul)) {
+ TCGv_i64 t1;
+
if (s->vl_eq_vlmax) {
+ t1 = tcg_temp_new_i64();
+ /* NaN-box f[rs1] */
+ do_nanbox(s, t1, cpu_fpr[a->rs1]);
+
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+ MAXSZ(s), MAXSZ(s), t1);
mark_vs_dirty(s);
} else {
TCGv_ptr dest;
@@ -2477,15 +2483,21 @@ static bool trans_vfmv_v_f(DisasContext *s,
arg_vfmv_v_f *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ t1 = tcg_temp_new_i64();
+ /* NaN-box f[rs1] */
+ do_nanbox(s, t1, cpu_fpr[a->rs1]);
+
dest = tcg_temp_new_ptr();
desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+ fns[s->sew - 1](dest, t1, cpu_env, desc);
tcg_temp_free_ptr(dest);
mark_vs_dirty(s);
gen_set_label(over);
}
+ tcg_temp_free_i64(t1);
return true;
}
return false;
--
2.31.1
- [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, (continued)
- [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Alistair Francis, 2021/12/19
- [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, Alistair Francis, 2021/12/19
- [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction, Alistair Francis, 2021/12/19
- [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction, Alistair Francis, 2021/12/19
- [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction, Alistair Francis, 2021/12/20
- [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions, Alistair Francis, 2021/12/20
- [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions, Alistair Francis, 2021/12/20
- [PULL 40/88] target/riscv: rvv-1.0: iota instruction, Alistair Francis, 2021/12/20
- [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended, Alistair Francis, 2021/12/20
- [PULL 41/88] target/riscv: rvv-1.0: element index instruction, Alistair Francis, 2021/12/20
- [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction,
Alistair Francis <=
- [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions, Alistair Francis, 2021/12/20
- [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions, Alistair Francis, 2021/12/20
- [PULL 47/88] target/riscv: rvv-1.0: whole register move instructions, Alistair Francis, 2021/12/20
- [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, Alistair Francis, 2021/12/20
- [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions, Alistair Francis, 2021/12/20
- [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions, Alistair Francis, 2021/12/20
- [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, Alistair Francis, 2021/12/20
- [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, Alistair Francis, 2021/12/20
- [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions, Alistair Francis, 2021/12/20
- [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions, Alistair Francis, 2021/12/20