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[PATCH] target/mips: Fix DBALIGN DSP-R2 opcode 'byte position' field siz
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH] target/mips: Fix DBALIGN DSP-R2 opcode 'byte position' field size |
Date: |
Sat, 29 May 2021 15:05:19 +0200 |
Per the "MIPS® DSP Module for MIPS64 Architecture" manual (rev 3.02),
Figure 5.12 "SPECIAL3 Encoding of APPEND/DAPPEND Instruction Sub-class"
the byte position field ('bp') is 2 bits, not 3.
Cc: Jia Liu <proljc@gmail.com>
Fixes: 26690560240 ("target-mips: Add ASE DSP compare-pick instructions")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index c03a8ae1fed..e68647ce14c 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -23016,8 +23016,8 @@ static void gen_mipsdsp_append(CPUMIPSState *env,
DisasContext *ctx,
}
break;
case OPC_DBALIGN:
- sa &= 7;
- if (sa != 0 && sa != 2 && sa != 4) {
+ sa &= 3;
+ if (sa != 0 && sa != 2) {
tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
tcg_gen_shri_tl(t0, t0, 8 * (8 - sa));
tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
--
2.26.3
- [PATCH] target/mips: Fix DBALIGN DSP-R2 opcode 'byte position' field size,
Philippe Mathieu-Daudé <=