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Re: [PATCH] target/mips: Fix DBALIGN DSP-R2 opcode 'byte position' field
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [PATCH] target/mips: Fix DBALIGN DSP-R2 opcode 'byte position' field size |
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Date: |
Mon, 31 May 2021 10:50:42 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 |
On 5/30/21 5:33 PM, Richard Henderson wrote:
> On 5/29/21 6:05 AM, Philippe Mathieu-Daudé wrote:
>> Per the "MIPS® DSP Module for MIPS64 Architecture" manual (rev 3.02),
>> Figure 5.12 "SPECIAL3 Encoding of APPEND/DAPPEND Instruction Sub-class"
>> the byte position field ('bp') is 2 bits, not 3.
>
> Rev 2.34 has 3 bits, not 2.
>
> The mips32 version of balign, that uses 2 bits... Are you sure you
> looked at the right instruction? Because 3 bits makes most sense for
> this instruction with a 64-bit register size.
Yes indeed it makes sense, and Rev 3.02 is incomplete...
Thanks,
Phil.