Richard Henderson <richard.henderson@linaro.org> writes:
Reorg everything using QEMU_GENERIC and multiple inclusion to
reduce the amount of code duplication between the formats.
The use of QEMU_GENERIC means that we need to use pointers instead
of structures, which means that even the smaller float formats
need rearranging.
I've carried it through to completion within fpu/, so that we don't
have (much) of the legacy code remaining. There is some floatx80
stuff in target/m68k and target/i386 that's still hanging around.
OK and here are some quad benchmarks. There is actual change above the
noise but I think the biggest hit comes from the parts conversion but we
do claw some of it back:
* Run Quad Benchmarks
#+name: run-quad-float-benchmarks
#+begin_src sh :results output table append
commit=$(git describe)
add=$(./tests/fp/fp-bench add -p quad)
mul=$(./tests/fp/fp-bench add -p quad)
muladd=$(./tests/fp/fp-bench add -p quad)
desc=$(git log --format="format:%s" HEAD^..)
echo "$commit,$add,$mul,$muladd,$desc"
#+end_src
#+RESULTS: run-quad-float-benchmarks
| pull-target-arm-20210510-1-91-g0fe775d52c | 90.28 MFlops | 90.15 MFlops |
90.75 MFlops | |
| pull-target-arm-20210510-1-92-gf7a6dabee2 | 90.80 MFlops | 89.92 MFlops |
90.66 MFlops | |
| pull-target-arm-20210510-1-93-gdb71c9fd28 | 88.93 MFlops | 89.10 MFlops |
87.32 MFlops | |
| pull-target-arm-20210510-1-93-gdb71c9fd28 | 88.85 MFlops | 88.83 MFlops |
88.53 MFlops | |
| pull-target-arm-20210510-1-94-g900ea1f79d | 87.10 MFlops | 88.02 MFlops |
88.22 MFlops | |
| pull-target-arm-20210510-1-95-gdb0bb2966f | 88.11 MFlops | 87.10 MFlops |
87.48 MFlops | softfloat: Tidy a * b + inf return |
| pull-target-arm-20210510-1-95-gdb0bb2966f | 87.27 MFlops | 84.86 MFlops |
87.99 MFlops | |
| pull-target-arm-20210510-1-95-gdb0bb2966f | 87.56 MFlops | 88.31 MFlops |
88.41 MFlops | softfloat: Tidy a * b + inf return |
| pull-target-arm-20210510-1-96-gec2be8ad0c | 88.12 MFlops | 88.88 MFlops |
89.09 MFlops | softfloat: Add float_cmask and constants |
| pull-target-arm-20210510-1-97-g2328f560a1 | 91.18 MFlops | 91.84 MFlops |
91.30 MFlops | softfloat: Use return_nan in float_to_float |
| pull-target-arm-20210510-1-97-g2328f560a1 | 90.07 MFlops | 91.16 MFlops |
91.14 MFlops | softfloat: Use return_nan in float_to_float |
| pull-target-arm-20210510-1-98-g89e2096c6f | 87.54 MFlops | 87.71 MFlops |
87.90 MFlops | softfloat: fix return_nan vs default_nan_mode |
| pull-target-arm-20210510-1-98-g89e2096c6f | 87.57 MFlops | 83.80 MFlops |
85.95 MFlops | softfloat: fix return_nan vs default_nan_mode |
| pull-target-arm-20210510-1-99-g67ceccacea | 89.29 MFlops | 87.46 MFlops |
87.40 MFlops | target/mips: Set set_default_nan_mode with set_snan_bit_is_one |
| pull-target-arm-20210510-1-99-g67ceccacea | 88.08 MFlops | 88.54 MFlops |
88.42 MFlops | target/mips: Set set_default_nan_mode with set_snan_bit_is_one |
| pull-target-arm-20210510-1-100-g8064a6d9d9 | 92.41 MFlops | 91.85 MFlops |
92.37 MFlops | softfloat: Do not produce a default_nan from parts_silence_nan |
| pull-target-arm-20210510-1-100-g8064a6d9d9 | 92.00 MFlops | 92.80 MFlops |
93.17 MFlops | softfloat: Do not produce a default_nan from parts_silence_nan |
| pull-target-arm-20210510-1-101-gc303832ddb | 92.27 MFlops | 91.76 MFlops |
91.56 MFlops | softfloat: Rename FloatParts to FloatParts64 |
| pull-target-arm-20210510-1-101-gc303832ddb | 92.64 MFlops | 92.73 MFlops |
92.54 MFlops | |
| pull-target-arm-20210510-1-110-g8c91cc4bfd | 94.34 MFlops | 93.50 MFlops |
94.00 MFlops | softfloat: Use pointers with parts_silence_nan |
| pull-target-arm-20210510-1-111-g039cab1333 | 94.72 MFlops | 95.36 MFlops |
94.67 MFlops | softfloat: Rearrange FloatParts64 |
| pull-target-arm-20210510-1-111-g039cab1333 | 94.55 MFlops | 94.99 MFlops |
95.13 MFlops | |
| pull-target-arm-20210510-1-111-g039cab1333 | 95.55 MFlops | 94.72 MFlops |
95.55 MFlops | |
| pull-target-arm-20210510-1-112-g5de6cec92b | 87.99 MFlops | 87.98 MFlops |
88.64 MFlops | softfloat: Convert float128_silence_nan to parts |
| pull-target-arm-20210510-1-112-g5de6cec92b | 87.20 MFlops | 88.26 MFlops |
88.04 MFlops | softfloat: Convert float128_silence_nan to parts |
| pull-target-arm-20210510-1-113-g6eb5e07c28 | 88.01 MFlops | 87.70 MFlops |
87.69 MFlops | softfloat: Convert float128_default_nan to parts |
| pull-target-arm-20210510-1-113-g6eb5e07c28 | 87.88 MFlops | 87.76 MFlops |
87.20 MFlops | softfloat: Convert float128_default_nan to parts |
| pull-target-arm-20210510-1-114-g7a4f7331e4 | 84.38 MFlops | 84.55 MFlops |
86.92 MFlops | softfloat: Move return_nan to softfloat-parts.c.inc |
| pull-target-arm-20210510-1-115-g08f1f1f3ed | 90.40 MFlops | 89.79 MFlops |
90.74 MFlops | softfloat: Move pick_nan to softfloat-parts.c.inc |
| pull-target-arm-20210510-1-115-g08f1f1f3ed | 90.74 MFlops | 90.11 MFlops |
90.59 MFlops | softfloat: Move pick_nan to softfloat-parts.c.inc |
| pull-target-arm-20210510-1-116-g474eb5be10 | 87.84 MFlops | 87.04 MFlops |
88.25 MFlops | softfloat: Move pick_nan_muladd to softfloat-parts.c.inc |
| pull-target-arm-20210510-1-116-g474eb5be10 | 88.22 MFlops | 87.79 MFlops |
88.10 MFlops | softfloat: Move pick_nan_muladd to softfloat-parts.c.inc |
| pull-target-arm-20210510-1-117-g096a466c23 | 86.37 MFlops | 85.32 MFlops |
86.22 MFlops | softfloat: Move sf_canonicalize to softfloat-parts.c.inc |
| pull-target-arm-20210510-1-118-g973977719f | 85.41 MFlops | 84.75 MFlops |
83.47 MFlops | softfloat: Move round_canonical to softfloat-parts.c.inc |
| pull-target-arm-20210510-1-119-g89c1fd4763 | 85.29 MFlops | 86.27 MFlops |
85.33 MFlops | softfloat: Use uadd64_carry/usub64_borrow in softfloat-macros.h |
| pull-target-arm-20210510-1-120-gfa24239a88 | 86.61 MFlops | 86.24 MFlops |
86.60 MFlops | softfloat: Move addsub_floats to softfloat-parts.c.inc |
| pull-target-arm-20210510-1-120-gfa24239a88 | 86.86 MFlops | 86.43 MFlops |
86.38 MFlops | |
| pull-target-arm-20210510-1-120-gfa24239a88 | 86.57 MFlops | 86.57 MFlops |
86.25 MFlops | |
| pull-target-arm-20210510-1-121-g15cf4c773a | 74.07 MFlops | 73.24 MFlops |
73.53 MFlops | |