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[PATCH 7/9] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_as
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 7/9] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0 |
Date: |
Sun, 9 May 2021 17:16:16 +0200 |
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
accel/tcg/cputlb.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index bc4370f4e21..47c83f0fc83 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -764,9 +764,8 @@ typedef struct {
uint16_t bits;
} TLBFlushRangeData;
-static void
-tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu,
- TLBFlushRangeData d)
+static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
+ TLBFlushRangeData d)
{
CPUArchState *env = cpu->env_ptr;
int mmu_idx;
@@ -814,14 +813,14 @@ decode_runon_to_pbm(run_on_cpu_data data)
static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu,
run_on_cpu_data runon)
{
- tlb_flush_page_bits_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon));
+ tlb_flush_range_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon));
}
static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu,
run_on_cpu_data data)
{
TLBFlushRangeData *d = data.host_ptr;
- tlb_flush_page_bits_by_mmuidx_async_0(cpu, *d);
+ tlb_flush_range_by_mmuidx_async_0(cpu, *d);
g_free(d);
}
@@ -853,7 +852,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong
addr,
d.bits = bits;
if (qemu_cpu_is_self(cpu)) {
- tlb_flush_page_bits_by_mmuidx_async_0(cpu, d);
+ tlb_flush_range_by_mmuidx_async_0(cpu, d);
} else if (encode_pbm_to_runon(&runon, d)) {
async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon);
} else {
@@ -913,7 +912,7 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu,
}
}
- tlb_flush_page_bits_by_mmuidx_async_0(src_cpu, d);
+ tlb_flush_range_by_mmuidx_async_0(src_cpu, d);
}
void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu,
--
2.26.3
- Re: [PATCH 1/9] accel/tcg: Replace g_new() + memcpy() by g_memdup(), (continued)
- [PATCH 2/9] accel/tcg: Pass length argument to tlb_flush_range_locked(), Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 3/9] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData, Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 4/9] accel/tcg: Add tlb_flush_range_by_mmuidx(), Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 5/9] accel/tcg: Add tlb_flush_page_bits_by_mmuidx_all_cpus(), Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 6/9] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced(), Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 7/9] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0,
Philippe Mathieu-Daudé <=
- [PATCH 8/9] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1], Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 9/9] accel/tcg: Remove tlb_flush_page_bits_by_mmuidx_async_1() ???, Philippe Mathieu-Daudé, 2021/05/09
- Re: [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages, Philippe Mathieu-Daudé, 2021/05/09
- Re: [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages, Peter Maydell, 2021/05/25