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[PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions
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From: |
Alistair Francis |
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Subject: |
[PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions |
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Date: |
Thu, 6 May 2021 09:22:41 +1000 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
---
target/riscv/csr.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1938bdca7d..6a39c4aa96 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -181,7 +181,11 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
static RISCVException hmode32(CPURISCVState *env, int csrno)
{
if (!riscv_cpu_is_32bit(env)) {
- return RISCV_EXCP_NONE;
+ if (riscv_cpu_virt_enabled(env)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ } else {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
}
return hmode(env, csrno);
--
2.31.1
- [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code, (continued)
- [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code, Alistair Francis, 2021/05/05
- [PULL v2 02/42] docs/system/generic-loader.rst: Fix style, Alistair Francis, 2021/05/05
- [PULL v2 03/42] target/riscv: Align the data type of reset vector address, Alistair Francis, 2021/05/05
- [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[], Alistair Francis, 2021/05/05
- [PULL v2 05/42] target/riscv: Add Shakti C class CPU, Alistair Francis, 2021/05/05
- [PULL v2 06/42] riscv: Add initial support for Shakti C machine, Alistair Francis, 2021/05/05
- [PULL v2 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/05
- [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/05
- [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/05
- [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/05
- [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions,
Alistair Francis <=
- [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/05
- [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/05
- [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/05
- [PULL v2 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/05
- [PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine, Alistair Francis, 2021/05/05
- [PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context, Alistair Francis, 2021/05/05
- [PULL v2 18/42] target/riscv: Fixup saturate subtract function, Alistair Francis, 2021/05/05
- [PULL v2 19/42] docs: Add documentation for shakti_c machine, Alistair Francis, 2021/05/05
- [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/05/05
- [PULL v2 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/05