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[PULL v2 18/42] target/riscv: Fixup saturate subtract function
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From: |
Alistair Francis |
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Subject: |
[PULL v2 18/42] target/riscv: Fixup saturate subtract function |
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Date: |
Thu, 6 May 2021 09:22:48 +1000 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
However, when the predication is ture and a is 0, it should return maximum.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a156573d28..356cef8a09 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2451,7 +2451,7 @@ static inline int8_t ssub8(CPURISCVState *env, int vxrm,
int8_t a, int8_t b)
{
int8_t res = a - b;
if ((res ^ a) & (a ^ b) & INT8_MIN) {
- res = a > 0 ? INT8_MAX : INT8_MIN;
+ res = a >= 0 ? INT8_MAX : INT8_MIN;
env->vxsat = 0x1;
}
return res;
@@ -2461,7 +2461,7 @@ static inline int16_t ssub16(CPURISCVState *env, int
vxrm, int16_t a, int16_t b)
{
int16_t res = a - b;
if ((res ^ a) & (a ^ b) & INT16_MIN) {
- res = a > 0 ? INT16_MAX : INT16_MIN;
+ res = a >= 0 ? INT16_MAX : INT16_MIN;
env->vxsat = 0x1;
}
return res;
@@ -2471,7 +2471,7 @@ static inline int32_t ssub32(CPURISCVState *env, int
vxrm, int32_t a, int32_t b)
{
int32_t res = a - b;
if ((res ^ a) & (a ^ b) & INT32_MIN) {
- res = a > 0 ? INT32_MAX : INT32_MIN;
+ res = a >= 0 ? INT32_MAX : INT32_MIN;
env->vxsat = 0x1;
}
return res;
@@ -2481,7 +2481,7 @@ static inline int64_t ssub64(CPURISCVState *env, int
vxrm, int64_t a, int64_t b)
{
int64_t res = a - b;
if ((res ^ a) & (a ^ b) & INT64_MIN) {
- res = a > 0 ? INT64_MAX : INT64_MIN;
+ res = a >= 0 ? INT64_MAX : INT64_MIN;
env->vxsat = 0x1;
}
return res;
--
2.31.1
- [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform, (continued)
- [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/05
- [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/05
- [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/05
- [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/05
- [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/05
- [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/05
- [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/05
- [PULL v2 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/05
- [PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine, Alistair Francis, 2021/05/05
- [PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context, Alistair Francis, 2021/05/05
- [PULL v2 18/42] target/riscv: Fixup saturate subtract function,
Alistair Francis <=
- [PULL v2 19/42] docs: Add documentation for shakti_c machine, Alistair Francis, 2021/05/05
- [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/05/05
- [PULL v2 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/05
- [PULL v2 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/05
- [PULL v2 23/42] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/05/05
- [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/05/05
- [PULL v2 25/42] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/05/05
- [PULL v2 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/05
- [PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/05
- [PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/05