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[PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
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From: |
Alistair Francis |
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Subject: |
[PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] |
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Date: |
Thu, 6 May 2021 09:22:34 +1000 |
From: Bin Meng <bmeng.cn@gmail.com>
This was accidentally dropped before. Add it back.
Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
Reported-by: Emmanuel Blot <eblot.ml@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210331103612.654261-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_e.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 3e8b44b2c0..ddc658c8d6 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -48,7 +48,7 @@
#include "sysemu/arch_init.h"
#include "sysemu/sysemu.h"
-static MemMapEntry sifive_e_memmap[] = {
+static const MemMapEntry sifive_e_memmap[] = {
[SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
[SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
[SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
--
2.31.1
- [PULL v2 00/42] riscv-to-apply queue, Alistair Francis, 2021/05/05
- [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code, Alistair Francis, 2021/05/05
- [PULL v2 02/42] docs/system/generic-loader.rst: Fix style, Alistair Francis, 2021/05/05
- [PULL v2 03/42] target/riscv: Align the data type of reset vector address, Alistair Francis, 2021/05/05
- [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[],
Alistair Francis <=
- [PULL v2 05/42] target/riscv: Add Shakti C class CPU, Alistair Francis, 2021/05/05
- [PULL v2 06/42] riscv: Add initial support for Shakti C machine, Alistair Francis, 2021/05/05
- [PULL v2 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/05
- [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/05
- [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/05
- [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/05
- [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/05
- [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/05
- [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/05
- [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/05