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| From: | Richard Henderson |
| Subject: | Re: [PATCH 03/27] tcg/aarch64: Fix generation of "scalar" vector operations |
| Date: | Fri, 5 Mar 2021 07:21:10 -0800 |
| User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 |
On 3/5/21 6:35 AM, Peter Maydell wrote:
None of these I36nn section numbers match up with the current Arm ARM, incidentally.
No, they're off the A.a document.
#define FMT_I3611(U, OPCODE) (0x5e200400 | ((U) << 29) | ((OPCODE) << 11)) and then I3611_SQADD = FMT_I3611(0, 0b00001), I3611_SQSUB = FMT_I3611(0, 0b00101), etc, instead of the raw I3611_SQADD = 0x5e200c00, I3611_SQSUB = 0x5e202c00,
Not a bad idea. r~
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