Re: [PATCH 03/27] tcg/aarch64: Fix generation of "scalar" vector operations

[Peter Maydell]

On Tue, 2 Mar 2021 at 18:00, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> For some vector operations, "1D" is not a valid type, and there
> are separate instructions for the 64-bit scalar operation.
>
> Tested-by: Stefan Weil <sw@weilnetz.de>
> Buglink: https://bugs.launchpad.net/qemu/+bug/1916112
> Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  tcg/aarch64/tcg-target.c.inc | 211 ++++++++++++++++++++++++++++++-----
>  1 file changed, 181 insertions(+), 30 deletions(-)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

None of these I36nn section numbers match up with the current Arm ARM,
incidentally.

I did wonder if it would be more readable/reviewable to have

#define FMT_I3611(U, OPCODE) (0x5e200400 | ((U) << 29) | ((OPCODE) << 11))

and then
  I3611_SQADD     = FMT_I3611(0, 0b00001),
  I3611_SQSUB     = FMT_I3611(0, 0b00101),

etc, instead of the raw
  I3611_SQADD     = 0x5e200c00,
  I3611_SQSUB     = 0x5e202c00,

But if you like that you can do it in a separate change :-)

thanks
-- PMM